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1368b914e9
Now that all port tests live under testsuite/sim/*/, and none live in testsuite/ directly, flatten the structure by moving all of the dirs under testsuite/sim/ to testsuite/ directly. We need to stop passing --tool to dejagnu so that it searches all dirs and not just ones that start with "sim". Since we have no other dirs in this tree, and no plans to add any, should be fine.
137 lines
3.3 KiB
ArmAsm
137 lines
3.3 KiB
ArmAsm
//Original:/testcases/core/c_dsp32shift_lmix/c_dsp32shift_lmix.dsp
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// Spec Reference: dsp32shift lshift: mix
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# mach: bfin
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.include "testutils.inc"
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start
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imm32 r4, 0x00000000;
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imm32 r5, 0x00000000;
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imm32 r6, 0x00000000;
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imm32 r7, 0x00000000;
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// lshift : positive data, count (+)=left (half reg)
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imm32 r0, 0x00010001;
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imm32 r1, 1;
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imm32 r2, 0x00020002;
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imm32 r3, 2;
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R4.H = LSHIFT R0.H BY R1.L;
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R4.L = LSHIFT R0.L BY R1.L; /* r4 = 0x00020002 */
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R5.H = LSHIFT R2.H BY R3.L;
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R5.L = LSHIFT R2.L BY R3.L; /* r5 = 0x00080008 */
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R6 = LSHIFT R0 BY R1.L (V); /* r6 = 0x00020002 */
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R7 = LSHIFT R2 BY R3.L (V); /* r7 = 0x00080008 */
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CHECKREG r4, 0x00020002;
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CHECKREG r5, 0x00080008;
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CHECKREG r6, 0x00020002;
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CHECKREG r7, 0x00080008;
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// lshift : (full reg)
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imm32 r1, 3;
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imm32 r3, 4;
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R6 = LSHIFT R0 BY R1.L; /* r6 = 0x00080010 */
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R7 = LSHIFT R2 BY R3.L;
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CHECKREG r6, 0x00080008; /* r7 = 0x00100010 */
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CHECKREG r7, 0x00200020;
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A0 = 0;
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A0.L = R0.L;
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A0.H = R0.H;
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A0 = LSHIFT A0 BY R1.L; /* a0 = 0x00080008 */
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R5 = A0.w; /* r5 = 0x00080008 */
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CHECKREG r5, 0x00080008;
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imm32 r4, 0x30000003;
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imm32 r1, 1;
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R6 = LSHIFT R4 BY R1.L; /* r5 = 0x60000006 */
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imm32 r1, 2;
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R7 = LSHIFT R4 BY R1.L; /* r5 = 0xc000000c like LSHIFT */
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CHECKREG r6, 0x60000006;
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CHECKREG r7, 0xc000000c;
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// lshift : count (-)=right (half reg)
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imm32 r0, 0x10001000;
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imm32 r1, -1;
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imm32 r2, 0x10001000;
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imm32 r3, -2;
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R4.H = LSHIFT R0.H BY R1.L;
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R4.L = LSHIFT R0.L BY R1.L; /* r4 = 0x08000800 */
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R5.H = LSHIFT R2.H BY R3.L;
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R5.L = LSHIFT R2.L BY R3.L; /* r4 = 0x04000400 */
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R6 = LSHIFT R0 BY R1.L (V); /* r4 = 0x08000800 */
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R7 = LSHIFT R2 BY R3.L (V); /* r4 = 0x04000400 */
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CHECKREG r4, 0x08000800;
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CHECKREG r5, 0x04000400;
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CHECKREG r6, 0x08000800;
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CHECKREG r7, 0x04000400;
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// lshift : (full reg)
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imm32 r1, -3;
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imm32 r3, -4;
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R6 = LSHIFT R0 BY R1.L; /* r6 = 0x02000200 */
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R7 = LSHIFT R2 BY R3.L; /* r7 = 0x01000100 */
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CHECKREG r6, 0x02000200;
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CHECKREG r7, 0x01000100;
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// NEGATIVE
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// lshift : NEGATIVE data, count (+)=left (half reg)
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imm32 r0, 0xc00f800f;
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imm32 r1, 1;
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imm32 r2, 0xe00fe00f;
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imm32 r3, 2;
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R4.H = LSHIFT R0.H BY R1.L;
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R4.L = LSHIFT R0.L BY R1.L; /* r4 = 0x801e001e */
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R5.H = LSHIFT R2.H BY R3.L;
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R5.L = LSHIFT R2.L BY R3.L; /* r4 = 0x803c803c */
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CHECKREG r4, 0x801e001e;
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CHECKREG r5, 0x803c803c;
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imm32 r0, 0xc80fe00f;
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imm32 r2, 0xe40fe00f;
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imm32 r1, 4;
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imm32 r3, 5;
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R6 = LSHIFT R0 BY R1.L; /* r6 = 0x80fe00f0 */
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R7 = LSHIFT R2 BY R3.L; /* r7 = 0x81fc01e0 */
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CHECKREG r6, 0x80fe00f0;
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CHECKREG r7, 0x81fc01e0;
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imm32 r0, 0xf80fe00f;
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imm32 r2, 0xfc0fe00f;
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R6 = LSHIFT R0 BY R1.L; /* r6 = 0x80fe00f0 */
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R7 = LSHIFT R2 BY R3.L; /* r7 = 0x81fc01e0 */
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CHECKREG r6, 0x80fe00f0;
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CHECKREG r7, 0x81fc01e0;
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// lshift : NEGATIVE data, count (-)=right (half reg) Working ok
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imm32 r0, 0x80f080f0;
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imm32 r1, -1;
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imm32 r2, 0x80f080f0;
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imm32 r3, -2;
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R4.H = LSHIFT R0.H BY R1.L;
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R4.L = LSHIFT R0.L BY R1.L; /* r4 = 0x40784078 */
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R5.H = LSHIFT R2.H BY R3.L;
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R5.L = LSHIFT R2.L BY R3.L; /* r4 = 0x203c203c */
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CHECKREG r4, 0x40784078;
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CHECKREG r5, 0x203c203c;
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R6 = LSHIFT R0 BY R1.L (V); /* r6 = 0x40784078 */
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R7 = LSHIFT R2 BY R3.L (V); /* r7 = 0x203c203c */
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CHECKREG r6, 0x40784078;
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CHECKREG r7, 0x203c203c;
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// lshift : (full reg)
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imm32 r1, -3;
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imm32 r3, -4;
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R6 = LSHIFT R0 BY R1.L; /* r6 = 0x101e101e */
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R7 = LSHIFT R2 BY R3.L; /* r7 = 0x080f080f */
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CHECKREG r6, 0x101e101e;
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CHECKREG r7, 0x080f080f;
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pass
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