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1368b914e9
Now that all port tests live under testsuite/sim/*/, and none live in testsuite/ directly, flatten the structure by moving all of the dirs under testsuite/sim/ to testsuite/ directly. We need to stop passing --tool to dejagnu so that it searches all dirs and not just ones that start with "sim". Since we have no other dirs in this tree, and no plans to add any, should be fine.
115 lines
3.0 KiB
ArmAsm
115 lines
3.0 KiB
ArmAsm
//Original:/testcases/core/c_dsp32mac_mix/c_dsp32mac_mix.dsp
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// Spec Reference: dsp32mac mix
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# mach: bfin
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.include "testutils.inc"
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start
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imm32 r0, 0xab235675;
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imm32 r1, 0xcfba5127;
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imm32 r2, 0x13246705;
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imm32 r3, 0x00060007;
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imm32 r4, 0x90abcd09;
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imm32 r5, 0x10acefdb;
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imm32 r6, 0x000c000d;
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imm32 r7, 0x1246700f;
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A1 = A0 = 0;
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A0.L = R0.L;
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A0.H = R0.H;
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// test the ROUNDING only on signed fraction T=1
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R0.H = (A1 = R4.L * R5.L), R0.L = (A0 = R4.L * R5.H) (T);
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R1.H = (A1 = R4.H * R5.L), R1.L = (A0 = R4.H * R5.H) (T);
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R2.H = (A1 = R6.L * R7.L), R2.L = (A0 = R6.H * R7.H) (T);
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R3.H = (A1 = R6.L * R7.H), R3.L = (A0 = R6.L * R7.L) (T);
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CHECKREG r0, 0x066DF95C;
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CHECKREG r1, 0x0E0AF17F;
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CHECKREG r2, 0x000B0001;
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CHECKREG r3, 0x0001000B;
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// When two results are stored to a single register, they must be rounded
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// or truncated and stored to the 2 halves of a single destination reg dst
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imm32 r0, 0x13545abd;
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imm32 r1, 0xadbcfec7;
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imm32 r2, 0xa1245679;
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imm32 r3, 0x00060007;
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imm32 r4, 0xefbc4569;
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imm32 r5, 0x1235000b;
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imm32 r6, 0x000c000d;
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imm32 r7, 0x678e000f;
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// The result accumulated in A0 and A1, and stored to a reg half
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R2.H = ( A1 = R1.L * R0.H ), A0 = R1.H * R0.L;
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R3.H = A1 , A0 = R7.H * R6.L (T);
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R4.H = ( A1 = R3.L * R2.H ) (M), A0 = R3.H * R2.L;
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A1 = R1.L * R0.H, R5.L = ( A0 = R1.H * R0.L ) (ISS2);
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CHECKREG r2, 0xFFD15679;
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CHECKREG r3, 0xFFD00007;
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CHECKREG r4, 0x00074569;
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CHECKREG r5, 0x12358000;
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imm32 r0, 0x13545abd;
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imm32 r1, 0xadbcfec7;
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imm32 r2, 0xa1245679;
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imm32 r3, 0x00060007;
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imm32 r4, 0xefbc4569;
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imm32 r5, 0x1235000b;
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imm32 r6, 0x000c000d;
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imm32 r7, 0x678e000f;
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// The result accumulated in A0 and A1, and stored to a reg
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R5.H = (A1 = R1.L * R0.H), R5.L = (A0 = R1.H * R0.L) (TFU);
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R6.H = (A1 = R3.L * R2.H) (M), R6.L = (A0 = R3.H * R2.L) (TFU);
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R7.H = (A1 = R1.L * R0.H) (M), R7.L = (A0 = R1.H * R0.L) (IH); // hi-word extraction
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CHECKREG r5, 0x133C3D94;
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CHECKREG r6, 0x00040002;
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CHECKREG r7, 0xFFE8E2D7;
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// The result accumulated in A0 and A1, and stored to a reg pair
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imm32 r0, 0x13545abd;
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imm32 r1, 0xadbcfec7;
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imm32 r2, 0xa1245679;
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imm32 r3, 0x00060007;
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imm32 r4, 0xefbc4569;
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imm32 r5, 0x1235000b;
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imm32 r6, 0x000c000d;
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imm32 r7, 0x678e000f;
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R3 = ( A1 = R1.L * R0.H ), A0 = R1.H * R0.L;
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R5 = ( A1 = R1.L * R0.H );
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R7 = ( A1 += R1.L * R0.H ) (M), A0 -= R1.H * R0.L;
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CHECKREG r2, 0xA1245679;
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CHECKREG r3, 0xFFD0BC98;
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CHECKREG r4, 0xEFBC4569;
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CHECKREG r5, 0xFFD0BC98;
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CHECKREG r6, 0x000C000D;
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CHECKREG r7, 0xFFB91AE4;
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A1 = R1.L * R0.H, R2 = ( A0 = R1.H * R0.L );
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A1 = R1.L * R0.H (M), R6 = ( A0 -= R1.H * R0.L );
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CHECKREG r2, 0xC5AEB798;
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CHECKREG r3, 0xFFD0BC98;
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CHECKREG r4, 0xEFBC4569;
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CHECKREG r5, 0xFFD0BC98;
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CHECKREG r6, 0x00000000;
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CHECKREG r7, 0xFFB91AE4;
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imm32 r0, 0x13545abd;
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imm32 r1, 0xadbcfec7;
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imm32 r2, 0xa1245679;
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imm32 r3, 0x00060007;
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imm32 r4, 0xefbc4569;
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imm32 r5, 0x1235000b;
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imm32 r6, 0x000c000d;
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imm32 r7, 0x678e000f;
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R3 = ( A1 -= R5.L * R4.H ), R2 = ( A0 -= R5.H * R4.L ) (S2RND);
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R3 = ( A1 -= R1.L * R0.H ) (M), R2 = ( A0 += R1.H * R0.L ) (S2RND);
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CHECKREG r2, 0x80000000;
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CHECKREG r3, 0x0002CBB0;
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pass
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