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1368b914e9
Now that all port tests live under testsuite/sim/*/, and none live in testsuite/ directly, flatten the structure by moving all of the dirs under testsuite/sim/ to testsuite/ directly. We need to stop passing --tool to dejagnu so that it searches all dirs and not just ones that start with "sim". Since we have no other dirs in this tree, and no plans to add any, should be fine.
387 lines
6.3 KiB
ArmAsm
387 lines
6.3 KiB
ArmAsm
// Test ALU RND RND12 RND20
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# mach: bfin
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#include "test.h"
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.include "testutils.inc"
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start
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R7 = 0;
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ASTAT = R7;
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// 7ffffff0
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// + 00008000
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// -> 7fff0000
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R0 = 0xfff0 (Z);
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R0.H = 0x7fff;
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R7.L = R0 (RND);
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R0 = ASTAT;
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CHECKREG R7, 0x7fff;
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CHECKREG R0, (_VS|_V|_V_COPY);
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// 7ffffff0
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// + 00008000
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// -> 7fff0000
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R0.L = 0xfff0;
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R0.H = 0x7fff;
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R7.H = R0 (RND);
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R0 = ASTAT;
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CHECKREG R7, 0x7fff7fff;
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CHECKREG R0, (_VS|_V|_V_COPY);
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// 7ff0fff0
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// + 00008000
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// -> 7ff10000
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R0.L = 0xfff0;
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R0.H = 0x7ff0;
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R7.L = R0 (RND);
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R0 = ASTAT;
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CHECKREG R7, 0x7fff7ff1
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CHECKREG R0, (_VS);
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// 7ff0fff0
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// + 00008000
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// -> 7ff10000
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// 7ff0fff0
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// + 8000
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// -> 7ff1
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R0.L = 0xfff0;
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R0.H = 0x7ff0;
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R7.H = R0 (RND);
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R0 = ASTAT;
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CHECKREG R7, 0x7ff17ff1
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CHECKREG R0, (_VS);
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// fffffff0
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// + 00008000
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// -> 00000000
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R0.L = 0xfff0;
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R0.H = 0xffff;
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R7.L = R0 (RND);
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R0 = ASTAT;
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CHECKREG R7, 0x7ff10000;
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CHECKREG R0, (_VS|_AZ);
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// fffffff0
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// + 00008000
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// -> 00000000
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R0.L = 0xfff0;
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R0.H = 0xffff;
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R7.H = R0 (RND);
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R0 = ASTAT;
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DBGA ( R7.H , 0 );
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CHECKREG R0, (_VS|_AZ);
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// 00fffff0
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// + 00008000
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// -> 0100
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R0.L = 0xfff0;
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R0.H = 0x00ff;
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R7.L = R0 (RND);
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R0 = ASTAT;
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DBGA ( R7.L , 0x0100 );
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CHECKREG R0, (_VS);
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// RND12
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// 07ffe000
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// + 00000000
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// = 07ffe000
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// + 00000800
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// -> 7ffe
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R0.L = 0xe000;
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R0.H = 0x07ff;
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R1 = 0x0000 (Z);
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R1.H = 0x0000;
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R7.L = R0 + R1 (RND12);
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R0 = ASTAT;
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DBGA ( R7.L , 0x7ffe );
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CHECKREG R0, (_VS);
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// 07ffff00
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// + 00000000
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// = 07ffff00
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// + 00000800
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// -> 7fff
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R0.L = 0xff00;
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R0.H = 0x07ff;
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R1.L = 0x0000;
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R1.H = 0x0000;
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R7.L = R0 + R1 (RND12);
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R0 = ASTAT;
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DBGA ( R7.L , 0x7fff );
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CHECKREG R0, (_VS|_V|_V_COPY);
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// 07fffc00
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// + 00000f00
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// = 08000b00
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// + 00000800
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// -> 7fff
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R0.L = 0xfc00;
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R0.H = 0x07ff;
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R1.L = 0x0f00;
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R1.H = 0x0000;
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R7.L = R0 + R1 (RND12);
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R0 = ASTAT;
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DBGA ( R7.L , 0x7fff );
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CHECKREG R0, (_VS|_V|_V_COPY);
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// 07ff c000
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// + 0000 1000
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// = 07ff d000
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// + 0000 0800
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// -> 7ff d
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R0.L = 0xc000;
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R0.H = 0x07ff;
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R1.L = 0x1000;
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R1.H = 0x0000;
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_DBG ASTAT;
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R7.L = R0 + R1 (RND12);
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_DBG ASTAT;
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R0 = ASTAT;
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_DBG R0;
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DBGA ( R7.L , 0x7ffd );
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CHECKREG R0, (_VS);
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// ffff ffea
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// + 07ff fe00
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// = 107ff fdea
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// + 0000 0800
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// -> 7ff f
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R0.L = 0xffea;
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R0.H = 0xffff;
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R1.L = 0xfe00;
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R1.H = 0x07ff;
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_DBG ASTAT;
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R7.L = R0 + R1 (RND12);
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_DBG ASTAT;
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R0 = ASTAT;
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_DBG R0;
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DBGA ( R7.L , 0x7fff );
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CHECKREG R0, (_VS|_V|_V_COPY);
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// Small negative plus small negative should give zero
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// ffff ffff
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// + ffff ffff
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// + 0000 0800
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// -> 000 0
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R0.L = 0xffff;
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R0.H = 0xffff;
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R1.L = 0xffff;
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R1.H = 0xffff;
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_DBG ASTAT;
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R7.L = R0 + R1 (RND12);
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R0 = ASTAT;
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_DBG R0;
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DBGA ( R7.L , 0x0000 );
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CHECKREG R0, (_VS|_AZ);
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// Small negative minus small positive should give zero
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// ffff ffff
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// + 0000 0001
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// - 0000 0800
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// -> 000 0
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R0.L = 0xffff;
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R0.H = 0xffff;
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R1.L = 0x0001;
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R1.H = 0x0000;
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R7.L = R0 - R1 (RND12);
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R0 = ASTAT;
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DBGA ( R7.L , 0x0000 );
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CHECKREG R0, (_VS|_AZ);
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// Large positive plus large positive should give maxpos
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// 07ff ffff
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// + 07ff ffff
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// + 0000 0800
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// -> 7ff f
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R0.L = 0xffff;
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R0.H = 0x07ff;
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R1.L = 0xffff;
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R1.H = 0x07ff;
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R7.L = R0 + R1 (RND12);
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R0 = ASTAT;
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DBGA ( R7.L , 0x7fff );
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CHECKREG R0, (_VS|_V|_V_COPY);
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// Large negative plus large negative should give maxneg
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// 0800 0000
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// + 0800 0000
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// + 0000 0800
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// -> 800 0
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R0.L = 0x0000;
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R0.H = 0x0800;
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R1.L = 0x0000;
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R1.H = 0x0800;
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R7.L = R0 + R1 (RND12);
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R0 = ASTAT;
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DBGA ( R7.L , 0x7fff );
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CHECKREG R0, (_VS|_V|_V_COPY);
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// Large positive minus large negative should give maxpos
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// 07ff ffff
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// - 0800 0000
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// + 0000 0800
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// -> 800 0
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R0.L = 0xffff;
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R0.H = 0x07ff;
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R1.L = 0x0000;
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R1.H = 0x0800;
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R7.L = R0 - R1 (RND12);
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R0 = ASTAT;
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_DBG ASTAT;
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DBGA ( R7.L , 0x0 );
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CHECKREG R0, (_VS|_AZ);
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// Large negative minus large positive should give maxneg
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// 0800 0000
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// - 07ff ffff
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// + 0000 0800
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// -> 800 0
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R0.L = 0x0000;
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R0.H = 0x0800;
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R1.L = 0xffff;
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R1.H = 0x07ff;
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R7.L = R0 - R1 (RND12);
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R0 = ASTAT;
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_DBG ASTAT;
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DBGA ( R7.L , 0x0000 );
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CHECKREG R0, (_VS|_AZ);
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// cef4 3ed6
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// - 56f4 417a
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// + 0000 0800
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// -> 800 0
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R0.L = 0x3ed6;
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R0.H = 0xcef4;
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R1.L = 0x417a;
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R1.H = 0x56f4;
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R7.L = R0 - R1 (RND12);
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R0 = ASTAT;
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DBGA ( R7.L , 0x8000 );
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CHECKREG R0, (_VS|_V|_V_COPY|_AN);
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// RND20
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// 00ff 0000
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// + 0000 0000
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// + 0008 0000
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// ->0010
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R0.L = 0x0000;
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R0.H = 0x00ff;
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R1.L = 0x0000;
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R1.H = 0x0000;
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R7.L = R0 + R1 (RND20);
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R0 = ASTAT;
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DBGA ( R7.L , 0x0010 );
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CHECKREG R0, (_VS);
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// 00f0 0000
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// + 000f 0000
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// + 0008 0000
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// ->0010
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R0.L = 0x0000;
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R0.H = 0x00f0;
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R1.L = 0x0000;
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R1.H = 0x000f;
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R7.L = R0 + R1 (RND20);
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R0 = ASTAT;
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DBGA ( R7.L , 0x0010 );
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CHECKREG R0, (_VS);
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// 7ff0 0000
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// + 0000 0000
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// + 0008 0000
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// ->07ff
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R0.L = 0x0000;
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R0.H = 0x7ff0;
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R1.L = 0x0000;
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R1.H = 0x0000;
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R7.L = R0 + R1 (RND20);
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R0 = ASTAT;
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DBGA ( R7.L , 0x07ff );
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CHECKREG R0, (_VS);
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// 7fff 0000
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// + 0000 0000
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// + 0008 0000
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// ->0800
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R0.L = 0x0000;
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R0.H = 0x7fff;
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R1.L = 0x0000;
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R1.H = 0x0000;
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R7.L = R0 + R1 (RND20);
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R0 = ASTAT;
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DBGA ( R7.L , 0x0800 );
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CHECKREG R0, (_VS);
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// ffff 0000
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// + 0000 0000
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// + 0008 0000
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// ->0000
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R0.L = 0x0000;
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R0.H = 0xffff;
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R1.L = 0x0000;
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R1.H = 0x0000;
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R7.L = R0 + R1 (RND20);
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R0 = ASTAT;
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DBGA ( R7.L , 0x0000 );
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DBGA ( R0.H , 0x0200 );
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DBGA ( R0.L , 0x0001 );
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// ff00 0000
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// + 0010 0000
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// + 0008 0000
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// ->fff1
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R0.L = 0x0000;
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R0.H = 0xff00;
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R1.L = 0x0000;
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R1.H = 0x0010;
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R7.L = R0 + R1 (RND20);
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R0 = ASTAT;
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DBGA ( R7.L , 0xfff1 );
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CHECKREG R0, (_VS|_AN);
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// ff00 0000
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// + 0018 0000
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// + 0008 0000
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// ->fff2
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R0.L = 0x0000;
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R0.H = 0xff00;
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R1.L = 0x0000;
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R1.H = 0x0018;
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R7.L = R0 + R1 (RND20);
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R0 = ASTAT;
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DBGA ( R7.L , 0xfff2 );
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CHECKREG R0, (_VS|_AN);
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// Small negative plus small negative should give zero
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// ffff ffff
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// + ffff ffff
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// + 0008 0000
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// ->0000
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R0.L = 0xffff;
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R0.H = 0xffff;
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R1.L = 0xffff;
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R1.H = 0xffff;
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R7.L = R0 + R1 (RND20);
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R0 = ASTAT;
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DBGA ( R7.L , 0x0000 );
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CHECKREG R0, (_VS|_AZ);
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// Small negative minus small positive should give zero
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// ffff ffff
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// + 0000 0010
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// + 0008 0000
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// ->0000
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R0.L = 0xffff;
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R0.H = 0xffff;
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R1.L = 0x0010;
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R1.H = 0x0000;
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R7.L = R0 - R1 (RND20);
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R0 = ASTAT;
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DBGA ( R7.L , 0x0000 );
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CHECKREG R0, (_VS|_AZ);
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pass
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