Jaydeep Patil 3224e32fb8 sim: riscv: Add support for compressed integer instructions ... Added support for simulation of compressed integer instruction set ("c"). Added test file sim/testsuite/riscv/c-ext.s to test compressed instructions. The compressed instructions are available for models implementing C extension. Such as RV32IC, RV64IC, RV32GC, RV64GC etc. Approved-By: Andrew Burgess <aburgess@redhat.com>		2024-02-13 11:04:04 +00:00
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acinclude.m4	Update copyright year range in header of all files managed by GDB	2024-01-12 15:49:57 +00:00
ChangeLog-2021	sim: rename ChangeLog files to ChangeLog-2021	2021-08-17 20:27:36 -04:00
interp.c	Update copyright year range in header of all files managed by GDB	2024-01-12 15:49:57 +00:00
local.mk	Update copyright year range in header of all files managed by GDB	2024-01-12 15:49:57 +00:00
machs.c	Update copyright year range in header of all files managed by GDB	2024-01-12 15:49:57 +00:00
machs.h	Update copyright year range in header of all files managed by GDB	2024-01-12 15:49:57 +00:00
model_list.def	sim: riscv: Add support for compressed integer instructions	2024-02-13 11:04:04 +00:00
riscv-sim.h	Update copyright year range in header of all files managed by GDB	2024-01-12 15:49:57 +00:00
sim-main.c	sim: riscv: Add support for compressed integer instructions	2024-02-13 11:04:04 +00:00
sim-main.h	Update copyright year range in header of all files managed by GDB	2024-01-12 15:49:57 +00:00