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09478dc331
']' characters into the output stream.
* v850-opc.c (v850_opcodes: Remove size field from all opcodes.
Add "memop" field to all opcodes (for the disassembler).
Reorder opcodes so that "nop" comes before "mov" and "jr"
comes before "jarl".
Should give us a functional disassembler.
409 lines
11 KiB
C
409 lines
11 KiB
C
#include "ansidecl.h"
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#include "opcode/v850.h"
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/* Local insertion and extraction functions. */
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static unsigned long insert_d9 PARAMS ((unsigned long, long, const char **));
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static long extract_d9 PARAMS ((unsigned long, int *));
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static unsigned long insert_d22 PARAMS ((unsigned long, long, const char **));
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static long extract_d22 PARAMS ((unsigned long, int *));
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static unsigned long insert_d16_15 PARAMS ((unsigned long, long,
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const char **));
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static long extract_d16_15 PARAMS ((unsigned long, int *));
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static unsigned long insert_d8_7 PARAMS ((unsigned long, long, const char **));
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static long extract_d8_7 PARAMS ((unsigned long, int *));
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static unsigned long insert_d8_6 PARAMS ((unsigned long, long, const char **));
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static long extract_d8_6 PARAMS ((unsigned long, int *));
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/* regular opcode */
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#define OP(x) ((x & 0x3f) << 5)
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#define OP_MASK OP(0x3f)
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/* conditional branch opcode */
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#define BOP(x) ((0x0b << 7) | (x & 0x0f))
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#define BOP_MASK ((0x0f << 7) | 0x0f)
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/* one-word opcodes */
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#define one(x) ((unsigned int) (x))
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/* two-word opcodes */
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#define two(x,y) ((unsigned int) (x) | ((unsigned int) (y) << 16))
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const struct v850_operand v850_operands[] = {
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#define UNUSED 0
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{ 0, 0, 0, 0, 0 },
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/* The R1 field in a format 1, 6, 7, or 9 insn. */
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#define R1 (UNUSED+1)
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{ 5, 0, 0, 0, V850_OPERAND_REG },
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/* The R2 field in a format 1, 2, 4, 5, 6, 7, 9 insn. */
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#define R2 (R1+1)
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{ 5, 11, 0, 0, V850_OPERAND_REG },
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/* The IMM5 field in a format 2 insn. */
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#define I5 (R2+1)
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{ 5, 0, 0, 0, V850_OPERAND_SIGNED },
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#define I5U (I5+1)
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{ 5, 0, 0, 0, 0 },
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/* The IMM16 field in a format 6 insn. */
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#define I16 (I5U+1)
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{ 16, 16, 0, 0, V850_OPERAND_SIGNED },
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/* The signed DISP7 field in a format 4 insn. */
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#define D7 (I16+1)
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{ 7, 0, 0, 0, 0},
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/* The DISP9 field in a format 3 insn. */
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#define D9 (D7+1)
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{ 9, 0, insert_d9, extract_d9, V850_OPERAND_SIGNED },
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/* The DISP16 field in a format 6 insn. */
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#define D16_15 (D9+1)
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{ 16, 16, insert_d16_15, extract_d16_15, V850_OPERAND_SIGNED },
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/* The DISP22 field in a format 4 insn. */
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#define D22 (D16_15+1)
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{ 22, 0, insert_d22, extract_d22, V850_OPERAND_SIGNED },
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#define B3 (D22+1)
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/* The 3 bit immediate field in format 8 insn. */
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{ 3, 11, 0, 0, 0 },
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#define CCCC (B3+1)
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/* The 4 bit condition code in a setf instruction */
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{ 4, 0, 0, 0, V850_OPERAND_CC },
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/* The unsigned DISP8_7 field in a format 4 insn. */
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#define D8_7 (CCCC+1)
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{ 8, 0, insert_d8_7, extract_d8_7, 0 },
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/* The unsigned DISP8_6 field in a format 4 insn. */
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#define D8_6 (D8_7+1)
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{ 8, 0, insert_d8_6, extract_d8_6, 0 },
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/* System register operands. */
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#define SR1 (D8_6+1)
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{ 5, 0, 0, 0, V850_OPERAND_SRG },
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/* EP Register. */
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#define EP (SR1+1)
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{ 0, 0, 0, 0, V850_OPERAND_EP },
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/* The IMM16 field (unsigned0 in a format 6 insn. */
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#define I16U (EP+1)
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{ 16, 16, 0, 0, 0},
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/* The R2 field as a system register. */
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#define SR2 (I16U+1)
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{ 5, 11, 0, 0, V850_OPERAND_SRG },
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/* The DISP16 field in a format 8 insn. */
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#define D16 (SR2+1)
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{ 16, 16, 0, 0, V850_OPERAND_SIGNED },
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} ;
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/* reg-reg instruction format (Format I) */
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#define IF1 {R1, R2}
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/* imm-reg instruction format (Format II) */
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#define IF2 {I5, R2}
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/* conditional branch instruction format (Format III) */
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#define IF3 {D9}
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/* 16-bit load/store instruction (Format IV) */
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#define IF4A {D7, EP, R2}
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#define IF4B {R2, D7, EP}
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#define IF4C {D8_7, EP, R2}
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#define IF4D {R2, D8_7, EP}
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#define IF4E {D8_6, EP, R2}
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#define IF4F {R2, D8_6, EP}
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/* Jump instruction (Format V) */
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#define IF5 {D22}
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/* 3 operand instruction (Format VI) */
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#define IF6 {I16, R1, R2}
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/* 3 operand instruction (Format VI) */
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#define IF6U {I16U, R1, R2}
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/* 32-bit load/store half/word instruction (Format VII) */
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#define IF7A {D16_15, R1, R2}
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#define IF7B {R2, D16_15, R1}
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/* 32-bit load/store byte instruction (Format VII) */
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#define IF7C {D16, R1, R2}
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#define IF7D {R2, D16, R1}
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/* Bit manipulation function. */
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/* The opcode table.
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The format of the opcode table is:
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NAME OPCODE MASK { OPERANDS }
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NAME is the name of the instruction.
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OPCODE is the instruction opcode.
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MASK is the opcode mask; this is used to tell the disassembler
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which bits in the actual opcode must match OPCODE.
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OPERANDS is the list of operands.
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The disassembler reads the table in order and prints the first
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instruction which matches, so this table is sorted to put more
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specific instructions before more general instructions. It is also
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sorted by major opcode. */
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const struct v850_opcode v850_opcodes[] = {
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/* load/store instructions */
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{ "sld.b", one(0x0300), one(0x0780), IF4A, 1 },
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{ "sld.h", one(0x0400), one(0x0780), IF4C, 1 },
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{ "sld.w", one(0x0500), one(0x0781), IF4E, 1 },
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{ "sst.b", one(0x0380), one(0x0780), IF4B, 2 },
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{ "sst.h", one(0x0480), one(0x0780), IF4D, 2 },
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{ "sst.w", one(0x0501), one(0x0781), IF4F, 2 },
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{ "ld.b", two(0x0700,0x0000), two (0x07e0,0x0000), IF7C, 1 },
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{ "ld.h", two(0x0720,0x0000), two (0x07e0,0x0001), IF7A, 1 },
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{ "ld.w", two(0x0720,0x0001), two (0x07e0,0x0001), IF7A, 1 },
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{ "st.b", two(0x0740,0x0000), two (0x07e0,0x0000), IF7D, 2 },
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{ "st.h", two(0x0760,0x0000), two (0x07e0,0x0001), IF7B, 2 },
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{ "st.w", two(0x0760,0x0001), two (0x07e0,0x0001), IF7B, 2 },
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/* arithmetic operation instructions */
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{ "nop", one(0x00), one(0xffff), {0}, 0 },
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{ "mov", OP(0x00), OP_MASK, IF1, 0 },
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{ "mov", OP(0x10), OP_MASK, IF2, 0 },
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{ "movea", OP(0x31), OP_MASK, IF6, 0 },
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{ "movhi", OP(0x32), OP_MASK, IF6, 0 },
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{ "add", OP(0x0e), OP_MASK, IF1, 0 },
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{ "add", OP(0x12), OP_MASK, IF2, 0 },
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{ "addi", OP(0x30), OP_MASK, IF6, 0 },
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{ "sub", OP(0x0d), OP_MASK, IF1, 0 },
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{ "subr", OP(0x0c), OP_MASK, IF1, 0 },
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{ "mulh", OP(0x07), OP_MASK, IF1, 0 },
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{ "mulh", OP(0x17), OP_MASK, IF2, 0 },
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{ "mulhi", OP(0x37), OP_MASK, IF6, 0 },
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{ "divh", OP(0x02), OP_MASK, IF1, 0 },
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{ "cmp", OP(0x0f), OP_MASK, IF1, 0 },
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{ "cmp", OP(0x13), OP_MASK, IF2, 0 },
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{ "setf", two(0x07e0,0x0000), two(0x07f0,0xffff), {CCCC,R2}, 0 },
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/* saturated operation instructions */
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{ "satadd", OP(0x06), OP_MASK, IF1, 0 },
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{ "satadd", OP(0x11), OP_MASK, IF2, 0 },
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{ "satsub", OP(0x05), OP_MASK, IF1, 0 },
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{ "satsubi", OP(0x33), OP_MASK, IF6, 0 },
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{ "satsubr", OP(0x04), OP_MASK, IF1, 0 },
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/* logical operation instructions */
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{ "tst", OP(0x0b), OP_MASK, IF1, 0 },
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{ "or", OP(0x08), OP_MASK, IF1, 0 },
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{ "ori", OP(0x34), OP_MASK, IF6U, 0 },
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{ "and", OP(0x0a), OP_MASK, IF1, 0 },
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{ "andi", OP(0x36), OP_MASK, IF6U, 0 },
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{ "xor", OP(0x09), OP_MASK, IF1, 0 },
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{ "xori", OP(0x35), OP_MASK, IF6U, 0 },
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{ "not", OP(0x01), OP_MASK, IF1, 0 },
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{ "sar", OP(0x15), OP_MASK, {I5U, R2}, 0 },
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{ "sar", two(0x07e0,0x00a0), two(0x07e0,0xffff), {R1,R2}, 0 },
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{ "shl", OP(0x16), OP_MASK, {I5U, R2}, 0 },
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{ "shl", two(0x07e0,0x00c0), two(0x07e0,0xffff), {R1,R2}, 0 },
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{ "shr", OP(0x14), OP_MASK, {I5U, R2}, 0 },
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{ "shr", two(0x07e0,0x0080), two(0x07e0,0xffff), {R1,R2}, 0 },
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/* branch instructions */
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/* signed integer */
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{ "bgt", BOP(0xf), BOP_MASK, IF3, 0 },
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{ "bge", BOP(0xe), BOP_MASK, IF3, 0 },
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{ "blt", BOP(0x6), BOP_MASK, IF3, 0 },
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{ "ble", BOP(0x7), BOP_MASK, IF3, 0 },
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/* unsigned integer */
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{ "bh", BOP(0xb), BOP_MASK, IF3, 0 },
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{ "bnh", BOP(0x3), BOP_MASK, IF3, 0 },
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{ "bl", BOP(0x1), BOP_MASK, IF3, 0 },
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{ "bnl", BOP(0x9), BOP_MASK, IF3, 0 },
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/* common */
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{ "be", BOP(0x2), BOP_MASK, IF3, 0 },
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{ "bne", BOP(0xa), BOP_MASK, IF3, 0 },
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/* others */
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{ "bv", BOP(0x0), BOP_MASK, IF3, 0 },
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{ "bnv", BOP(0x8), BOP_MASK, IF3, 0 },
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{ "bn", BOP(0x4), BOP_MASK, IF3, 0 },
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{ "bp", BOP(0xc), BOP_MASK, IF3, 0 },
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{ "bc", BOP(0x1), BOP_MASK, IF3, 0 },
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{ "bnc", BOP(0x9), BOP_MASK, IF3, 0 },
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{ "bz", BOP(0x2), BOP_MASK, IF3, 0 },
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{ "bnz", BOP(0xa), BOP_MASK, IF3, 0 },
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{ "br", BOP(0x5), BOP_MASK, IF3, 0 },
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{ "bsa", BOP(0xd), BOP_MASK, IF3, 0 },
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{ "jmp", one(0x0060), one(0xffe0), { R1}, 1 },
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{ "jr", one(0x0780), two(0xffc0,0x0001),{ D22 }, 0 },
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{ "jarl", one(0x0780), two(0x07c0,0x0001),{ D22, R2 }, 0 },
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/* bit manipulation instructions */
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{ "set1", two(0x07c0,0x0000), two(0xc7e0,0x0000), {B3, D16, R1}, 2 },
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{ "not1", two(0x47c0,0x0000), two(0xc7e0,0x0000), {B3, D16, R1}, 2 },
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{ "clr1", two(0x87c0,0x0000), two(0xc7e0,0x0000), {B3, D16, R1}, 2 },
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{ "tst1", two(0xc7c0,0x0000), two(0xc7e0,0x0000), {B3, D16, R1}, 2 },
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/* special instructions */
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{ "di", two(0x07e0,0x0160), two(0xffff,0xffff), {0}, 0 },
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{ "ei", two(0x87e0,0x0160), two(0xffff,0xffff), {0}, 0 },
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{ "halt", two(0x07e0,0x0120), two(0xffff,0xffff), {0}, 0 },
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{ "reti", two(0x07e0,0x0140), two(0xffff,0xffff), {0}, 0 },
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{ "trap", two(0x07e0,0x0100), two(0xffe0,0xffff), {I5U}, 0 },
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{ "ldsr", two(0x07e0,0x0020), two(0x07e0,0xffff), {R1,SR2}, 0 },
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{ "stsr", two(0x07e0,0x0040), two(0x07e0,0xffff), {SR1,R2}, 0 },
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{ 0, 0, 0, {0}, 0 },
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} ;
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const int v850_num_opcodes =
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sizeof (v850_opcodes) / sizeof (v850_opcodes[0]);
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/* The functions used to insert and extract complicated operands. */
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static unsigned long
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insert_d9 (insn, value, errmsg)
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unsigned long insn;
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long value;
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const char **errmsg;
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{
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if (value > 255 || value <= -256)
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*errmsg = "branch value out of range";
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if ((value % 2) != 0)
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*errmsg = "branch to odd offset";
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return (insn | ((value & 0x1f0) << 7) | ((value & 0x0e) << 3));
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}
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static long
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extract_d9 (insn, invalid)
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unsigned long insn;
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int *invalid;
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{
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long ret = ((insn & 0xf800) >> 7) | ((insn & 0x0070) >> 3);
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if ((insn & 0x8000) != 0)
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ret -= 0x0200;
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return ret;
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}
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static unsigned long
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insert_d22 (insn, value, errmsg)
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unsigned long insn;
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long value;
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const char **errmsg;
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{
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if (value > 0xfffff || value <= -0x100000)
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*errmsg = "branch value out of range";
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if ((value % 2) != 0)
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*errmsg = "branch to odd offset";
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return (insn | ((value & 0xfffe) << 16) | ((value & 0x3f0000) >> 16));
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}
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static long
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extract_d22 (insn, invalid)
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unsigned long insn;
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int *invalid;
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{
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int ret = ((insn & 0xfffe0000) >> 16) | ((insn & 0x3f) << 16);
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return ((ret << 10) >> 10);
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}
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static unsigned long
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insert_d16_15 (insn, value, errmsg)
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unsigned long insn;
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long value;
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const char **errmsg;
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{
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if (value > 0x7fff || value <= -0x8000)
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*errmsg = "value out of range";
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if ((value % 2) != 0)
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*errmsg = "load/store half/word at odd offset";
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return (insn | ((value & 0xfffe) << 16));
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}
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static long
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extract_d16_15 (insn, invalid)
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unsigned long insn;
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int *invalid;
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{
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int ret = ((insn & 0xfffe0000) >> 16);
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return ((ret << 16) >> 16);
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}
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static unsigned long
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insert_d8_7 (insn, value, errmsg)
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unsigned long insn;
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long value;
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const char **errmsg;
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{
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if (value > 0xff || value < 0)
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*errmsg = "short load/store half value out of range";
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if ((value % 2) != 0)
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*errmsg = "short load/store half at odd offset";
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value >>= 1;
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return (insn | (value & 0x7f));
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}
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static long
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extract_d8_7 (insn, invalid)
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unsigned long insn;
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int *invalid;
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{
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int ret = (insn & 0x7f);
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return ret << 1;
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}
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static unsigned long
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insert_d8_6 (insn, value, errmsg)
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unsigned long insn;
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long value;
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const char **errmsg;
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{
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if (value > 0xff || value < 0)
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*errmsg = "short load/store word value out of range";
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if ((value % 4) != 0)
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*errmsg = "short load/store word at odd offset";
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value >>= 1;
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return (insn | (value & 0x7e));
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}
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static long
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extract_d8_6 (insn, invalid)
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unsigned long insn;
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int *invalid;
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{
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int ret = (insn & 0x7e);
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return ret << 1;
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}
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