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aa3c112fab
include/ * opcode/ppc.h (PPC_OPERAND_ACC): Define. Renumber following PPC_OPERAND defines. opcodes/ * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a): New functions. (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK, YMSK2, XA6a, XA6ap, XB6a entries. (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define. (PPCVSX4): Define. (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz, xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger, xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp, xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np, xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp, xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn, xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16. (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp, pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8, pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2, pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp, pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp, pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn, pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn. gas/ * config/tc-ppc.c (pre_defined_registers): Add accumulators. (md_assemble): Check acc specified in correct operand. * testsuite/gas/ppc/outerprod.d, * testsuite/gas/ppc/outerprod.s, * testsuite/gas/ppc/vsx4.d, * testsuite/gas/ppc/vsx4.s: New tests. * testsuite/gas/ppc/ppc.exp: Run them.
987 lines
30 KiB
C
987 lines
30 KiB
C
/* ppc-dis.c -- Disassemble PowerPC instructions
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Copyright (C) 1994-2020 Free Software Foundation, Inc.
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Written by Ian Lance Taylor, Cygnus Support
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This file is part of the GNU opcodes library.
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This library is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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It is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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You should have received a copy of the GNU General Public License
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along with this file; see the file COPYING. If not, write to the
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Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
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MA 02110-1301, USA. */
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#include "sysdep.h"
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#include <stdio.h>
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#include "disassemble.h"
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#include "elf-bfd.h"
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#include "elf/ppc.h"
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#include "opintl.h"
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#include "opcode/ppc.h"
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#include "libiberty.h"
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/* This file provides several disassembler functions, all of which use
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the disassembler interface defined in dis-asm.h. Several functions
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are provided because this file handles disassembly for the PowerPC
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in both big and little endian mode and also for the POWER (RS/6000)
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chip. */
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static int print_insn_powerpc (bfd_vma, struct disassemble_info *, int,
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ppc_cpu_t);
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struct dis_private
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{
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/* Stash the result of parsing disassembler_options here. */
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ppc_cpu_t dialect;
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};
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#define POWERPC_DIALECT(INFO) \
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(((struct dis_private *) ((INFO)->private_data))->dialect)
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struct ppc_mopt {
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/* Option string, without -m or -M prefix. */
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const char *opt;
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/* CPU option flags. */
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ppc_cpu_t cpu;
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/* Flags that should stay on, even when combined with another cpu
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option. This should only be used for generic options like
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"-many" or "-maltivec" where it is reasonable to add some
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capability to another cpu selection. The added flags are sticky
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so that, for example, "-many -me500" and "-me500 -many" result in
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the same assembler or disassembler behaviour. Do not use
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"sticky" for specific cpus, as this will prevent that cpu's flags
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from overriding the defaults set in powerpc_init_dialect or a
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prior -m option. */
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ppc_cpu_t sticky;
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};
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struct ppc_mopt ppc_opts[] = {
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{ "403", PPC_OPCODE_PPC | PPC_OPCODE_403,
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0 },
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{ "405", PPC_OPCODE_PPC | PPC_OPCODE_403 | PPC_OPCODE_405,
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0 },
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{ "440", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_440
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| PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI),
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0 },
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{ "464", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_440
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| PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI),
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0 },
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{ "476", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_476
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| PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5),
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0 },
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{ "601", PPC_OPCODE_PPC | PPC_OPCODE_601,
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0 },
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{ "603", PPC_OPCODE_PPC,
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0 },
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{ "604", PPC_OPCODE_PPC,
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0 },
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{ "620", PPC_OPCODE_PPC | PPC_OPCODE_64,
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0 },
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{ "7400", PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC,
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0 },
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{ "7410", PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC,
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0 },
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{ "7450", PPC_OPCODE_PPC | PPC_OPCODE_7450 | PPC_OPCODE_ALTIVEC,
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0 },
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{ "7455", PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC,
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0 },
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{ "750cl", PPC_OPCODE_PPC | PPC_OPCODE_750 | PPC_OPCODE_PPCPS
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, 0 },
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{ "gekko", PPC_OPCODE_PPC | PPC_OPCODE_750 | PPC_OPCODE_PPCPS
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, 0 },
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{ "broadway", PPC_OPCODE_PPC | PPC_OPCODE_750 | PPC_OPCODE_PPCPS
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, 0 },
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{ "821", PPC_OPCODE_PPC | PPC_OPCODE_860,
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0 },
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{ "850", PPC_OPCODE_PPC | PPC_OPCODE_860,
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0 },
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{ "860", PPC_OPCODE_PPC | PPC_OPCODE_860,
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0 },
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{ "a2", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_POWER4
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| PPC_OPCODE_POWER5 | PPC_OPCODE_CACHELCK | PPC_OPCODE_64
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| PPC_OPCODE_A2),
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0 },
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{ "altivec", PPC_OPCODE_PPC,
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PPC_OPCODE_ALTIVEC },
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{ "any", PPC_OPCODE_PPC,
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PPC_OPCODE_ANY },
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{ "booke", PPC_OPCODE_PPC | PPC_OPCODE_BOOKE,
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0 },
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{ "booke32", PPC_OPCODE_PPC | PPC_OPCODE_BOOKE,
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0 },
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{ "cell", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
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| PPC_OPCODE_CELL | PPC_OPCODE_ALTIVEC),
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0 },
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{ "com", PPC_OPCODE_COMMON,
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0 },
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{ "e200z4", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE| PPC_OPCODE_SPE
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| PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
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| PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
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| PPC_OPCODE_E500 | PPC_OPCODE_VLE | PPC_OPCODE_E200Z4
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| PPC_OPCODE_EFS2 | PPC_OPCODE_LSP),
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0 },
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{ "e300", PPC_OPCODE_PPC | PPC_OPCODE_E300,
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0 },
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{ "e500", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE
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| PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
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| PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
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| PPC_OPCODE_E500),
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0 },
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{ "e500mc", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
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| PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
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| PPC_OPCODE_E500MC),
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0 },
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{ "e500mc64", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
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| PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
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| PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_POWER5
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| PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7),
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0 },
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{ "e5500", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
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| PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
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| PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
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| PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7),
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0 },
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{ "e6500", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
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| PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
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| PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_ALTIVEC
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| PPC_OPCODE_E6500 | PPC_OPCODE_TMR | PPC_OPCODE_POWER4
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| PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7),
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0 },
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{ "e500x2", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE
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| PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
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| PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
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| PPC_OPCODE_E500),
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0 },
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{ "efs", PPC_OPCODE_PPC | PPC_OPCODE_EFS,
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0 },
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{ "efs2", PPC_OPCODE_PPC | PPC_OPCODE_EFS | PPC_OPCODE_EFS2,
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0 },
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{ "power4", PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4,
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0 },
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{ "power5", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
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| PPC_OPCODE_POWER5),
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0 },
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{ "power6", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
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| PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC),
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0 },
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{ "power7", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
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| PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
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| PPC_OPCODE_POWER7 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
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0 },
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{ "power8", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
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| PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
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| PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8
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| PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
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0 },
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{ "power9", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
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| PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
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| PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9
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| PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
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0 },
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{ "power10", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
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| PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
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| PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9
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| PPC_OPCODE_POWER10 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
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0 },
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{ "future", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
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| PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
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| PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9
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| PPC_OPCODE_POWER10 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
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0 },
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{ "ppc", PPC_OPCODE_PPC,
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0 },
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{ "ppc32", PPC_OPCODE_PPC,
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0 },
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{ "32", PPC_OPCODE_PPC,
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0 },
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{ "ppc64", PPC_OPCODE_PPC | PPC_OPCODE_64,
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0 },
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{ "64", PPC_OPCODE_PPC | PPC_OPCODE_64,
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0 },
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{ "ppc64bridge", PPC_OPCODE_PPC | PPC_OPCODE_64_BRIDGE,
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0 },
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{ "ppcps", PPC_OPCODE_PPC | PPC_OPCODE_PPCPS,
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0 },
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{ "pwr", PPC_OPCODE_POWER,
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0 },
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{ "pwr2", PPC_OPCODE_POWER | PPC_OPCODE_POWER2,
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0 },
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{ "pwr4", PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4,
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0 },
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{ "pwr5", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
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| PPC_OPCODE_POWER5),
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0 },
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{ "pwr5x", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
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| PPC_OPCODE_POWER5),
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0 },
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{ "pwr6", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
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| PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC),
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0 },
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{ "pwr7", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
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| PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
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| PPC_OPCODE_POWER7 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
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0 },
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{ "pwr8", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
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| PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
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| PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8
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| PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
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0 },
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{ "pwr9", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
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| PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
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| PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9
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| PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
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0 },
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{ "pwrx", PPC_OPCODE_POWER | PPC_OPCODE_POWER2,
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0 },
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{ "raw", PPC_OPCODE_PPC,
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PPC_OPCODE_RAW },
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{ "spe", PPC_OPCODE_PPC | PPC_OPCODE_EFS,
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PPC_OPCODE_SPE },
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{ "spe2", PPC_OPCODE_PPC | PPC_OPCODE_EFS | PPC_OPCODE_EFS2 | PPC_OPCODE_SPE,
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PPC_OPCODE_SPE2 },
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{ "titan", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_PMR
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| PPC_OPCODE_RFMCI | PPC_OPCODE_TITAN),
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0 },
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{ "vle", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE| PPC_OPCODE_SPE
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| PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
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| PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
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| PPC_OPCODE_LSP | PPC_OPCODE_EFS2 | PPC_OPCODE_SPE2),
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PPC_OPCODE_VLE },
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{ "vsx", PPC_OPCODE_PPC,
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PPC_OPCODE_VSX },
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};
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/* Switch between Booke and VLE dialects for interlinked dumps. */
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static ppc_cpu_t
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get_powerpc_dialect (struct disassemble_info *info)
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{
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ppc_cpu_t dialect = 0;
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if (info->private_data)
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dialect = POWERPC_DIALECT (info);
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/* Disassemble according to the section headers flags for VLE-mode. */
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if (dialect & PPC_OPCODE_VLE
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&& info->section != NULL && info->section->owner != NULL
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&& bfd_get_flavour (info->section->owner) == bfd_target_elf_flavour
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&& elf_object_id (info->section->owner) == PPC32_ELF_DATA
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&& (elf_section_flags (info->section) & SHF_PPC_VLE) != 0)
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return dialect;
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else
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return dialect & ~ PPC_OPCODE_VLE;
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}
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/* Handle -m and -M options that set cpu type, and .machine arg. */
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ppc_cpu_t
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ppc_parse_cpu (ppc_cpu_t ppc_cpu, ppc_cpu_t *sticky, const char *arg)
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{
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unsigned int i;
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for (i = 0; i < ARRAY_SIZE (ppc_opts); i++)
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if (disassembler_options_cmp (ppc_opts[i].opt, arg) == 0)
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{
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if (ppc_opts[i].sticky)
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{
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*sticky |= ppc_opts[i].sticky;
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if ((ppc_cpu & ~*sticky) != 0)
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break;
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}
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ppc_cpu = ppc_opts[i].cpu;
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break;
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}
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if (i >= ARRAY_SIZE (ppc_opts))
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return 0;
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ppc_cpu |= *sticky;
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return ppc_cpu;
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}
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/* Determine which set of machines to disassemble for. */
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static void
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powerpc_init_dialect (struct disassemble_info *info)
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{
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ppc_cpu_t dialect = 0;
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ppc_cpu_t sticky = 0;
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struct dis_private *priv = calloc (sizeof (*priv), 1);
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if (priv == NULL)
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return;
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switch (info->mach)
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{
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case bfd_mach_ppc_403:
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case bfd_mach_ppc_403gc:
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dialect = ppc_parse_cpu (dialect, &sticky, "403");
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break;
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case bfd_mach_ppc_405:
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dialect = ppc_parse_cpu (dialect, &sticky, "405");
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break;
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case bfd_mach_ppc_601:
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dialect = ppc_parse_cpu (dialect, &sticky, "601");
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break;
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case bfd_mach_ppc_750:
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dialect = ppc_parse_cpu (dialect, &sticky, "750cl");
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break;
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case bfd_mach_ppc_a35:
|
|
case bfd_mach_ppc_rs64ii:
|
|
case bfd_mach_ppc_rs64iii:
|
|
dialect = ppc_parse_cpu (dialect, &sticky, "pwr2") | PPC_OPCODE_64;
|
|
break;
|
|
case bfd_mach_ppc_e500:
|
|
dialect = ppc_parse_cpu (dialect, &sticky, "e500");
|
|
break;
|
|
case bfd_mach_ppc_e500mc:
|
|
dialect = ppc_parse_cpu (dialect, &sticky, "e500mc");
|
|
break;
|
|
case bfd_mach_ppc_e500mc64:
|
|
dialect = ppc_parse_cpu (dialect, &sticky, "e500mc64");
|
|
break;
|
|
case bfd_mach_ppc_e5500:
|
|
dialect = ppc_parse_cpu (dialect, &sticky, "e5500");
|
|
break;
|
|
case bfd_mach_ppc_e6500:
|
|
dialect = ppc_parse_cpu (dialect, &sticky, "e6500");
|
|
break;
|
|
case bfd_mach_ppc_titan:
|
|
dialect = ppc_parse_cpu (dialect, &sticky, "titan");
|
|
break;
|
|
case bfd_mach_ppc_vle:
|
|
dialect = ppc_parse_cpu (dialect, &sticky, "vle");
|
|
break;
|
|
default:
|
|
if (info->arch == bfd_arch_powerpc)
|
|
dialect = ppc_parse_cpu (dialect, &sticky, "power10") | PPC_OPCODE_ANY;
|
|
else
|
|
dialect = ppc_parse_cpu (dialect, &sticky, "pwr");
|
|
break;
|
|
}
|
|
|
|
const char *opt;
|
|
FOR_EACH_DISASSEMBLER_OPTION (opt, info->disassembler_options)
|
|
{
|
|
ppc_cpu_t new_cpu = 0;
|
|
|
|
if (disassembler_options_cmp (opt, "32") == 0)
|
|
dialect &= ~(ppc_cpu_t) PPC_OPCODE_64;
|
|
else if (disassembler_options_cmp (opt, "64") == 0)
|
|
dialect |= PPC_OPCODE_64;
|
|
else if ((new_cpu = ppc_parse_cpu (dialect, &sticky, opt)) != 0)
|
|
dialect = new_cpu;
|
|
else
|
|
/* xgettext: c-format */
|
|
opcodes_error_handler (_("warning: ignoring unknown -M%s option"), opt);
|
|
}
|
|
|
|
info->private_data = priv;
|
|
POWERPC_DIALECT(info) = dialect;
|
|
}
|
|
|
|
#define PPC_OPCD_SEGS (1 + PPC_OP (-1))
|
|
static unsigned short powerpc_opcd_indices[PPC_OPCD_SEGS + 1];
|
|
#define PREFIX_OPCD_SEGS (1 + PPC_PREFIX_SEG (-1))
|
|
static unsigned short prefix_opcd_indices[PREFIX_OPCD_SEGS + 1];
|
|
#define VLE_OPCD_SEGS (1 + VLE_OP_TO_SEG (VLE_OP (-1, 0xffff)))
|
|
static unsigned short vle_opcd_indices[VLE_OPCD_SEGS + 1];
|
|
#define SPE2_OPCD_SEGS (1 + SPE2_XOP_TO_SEG (SPE2_XOP (-1)))
|
|
static unsigned short spe2_opcd_indices[SPE2_OPCD_SEGS + 1];
|
|
|
|
/* Calculate opcode table indices to speed up disassembly,
|
|
and init dialect. */
|
|
|
|
void
|
|
disassemble_init_powerpc (struct disassemble_info *info)
|
|
{
|
|
if (powerpc_opcd_indices[PPC_OPCD_SEGS] == 0)
|
|
{
|
|
unsigned seg, idx, op;
|
|
|
|
/* PPC opcodes */
|
|
for (seg = 0, idx = 0; seg <= PPC_OPCD_SEGS; seg++)
|
|
{
|
|
powerpc_opcd_indices[seg] = idx;
|
|
for (; idx < powerpc_num_opcodes; idx++)
|
|
if (seg < PPC_OP (powerpc_opcodes[idx].opcode))
|
|
break;
|
|
}
|
|
|
|
/* 64-bit prefix opcodes */
|
|
for (seg = 0, idx = 0; seg <= PREFIX_OPCD_SEGS; seg++)
|
|
{
|
|
prefix_opcd_indices[seg] = idx;
|
|
for (; idx < prefix_num_opcodes; idx++)
|
|
if (seg < PPC_PREFIX_SEG (prefix_opcodes[idx].opcode))
|
|
break;
|
|
}
|
|
|
|
/* VLE opcodes */
|
|
for (seg = 0, idx = 0; seg <= VLE_OPCD_SEGS; seg++)
|
|
{
|
|
vle_opcd_indices[seg] = idx;
|
|
for (; idx < vle_num_opcodes; idx++)
|
|
{
|
|
op = VLE_OP (vle_opcodes[idx].opcode, vle_opcodes[idx].mask);
|
|
if (seg < VLE_OP_TO_SEG (op))
|
|
break;
|
|
}
|
|
}
|
|
|
|
/* SPE2 opcodes */
|
|
for (seg = 0, idx = 0; seg <= SPE2_OPCD_SEGS; seg++)
|
|
{
|
|
spe2_opcd_indices[seg] = idx;
|
|
for (; idx < spe2_num_opcodes; idx++)
|
|
{
|
|
op = SPE2_XOP (spe2_opcodes[idx].opcode);
|
|
if (seg < SPE2_XOP_TO_SEG (op))
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
powerpc_init_dialect (info);
|
|
}
|
|
|
|
/* Print a big endian PowerPC instruction. */
|
|
|
|
int
|
|
print_insn_big_powerpc (bfd_vma memaddr, struct disassemble_info *info)
|
|
{
|
|
return print_insn_powerpc (memaddr, info, 1, get_powerpc_dialect (info));
|
|
}
|
|
|
|
/* Print a little endian PowerPC instruction. */
|
|
|
|
int
|
|
print_insn_little_powerpc (bfd_vma memaddr, struct disassemble_info *info)
|
|
{
|
|
return print_insn_powerpc (memaddr, info, 0, get_powerpc_dialect (info));
|
|
}
|
|
|
|
/* Extract the operand value from the PowerPC or POWER instruction. */
|
|
|
|
static int64_t
|
|
operand_value_powerpc (const struct powerpc_operand *operand,
|
|
uint64_t insn, ppc_cpu_t dialect)
|
|
{
|
|
int64_t value;
|
|
int invalid = 0;
|
|
/* Extract the value from the instruction. */
|
|
if (operand->extract)
|
|
value = (*operand->extract) (insn, dialect, &invalid);
|
|
else
|
|
{
|
|
if (operand->shift >= 0)
|
|
value = (insn >> operand->shift) & operand->bitm;
|
|
else
|
|
value = (insn << -operand->shift) & operand->bitm;
|
|
if ((operand->flags & PPC_OPERAND_SIGNED) != 0)
|
|
{
|
|
/* BITM is always some number of zeros followed by some
|
|
number of ones, followed by some number of zeros. */
|
|
uint64_t top = operand->bitm;
|
|
/* top & -top gives the rightmost 1 bit, so this
|
|
fills in any trailing zeros. */
|
|
top |= (top & -top) - 1;
|
|
top &= ~(top >> 1);
|
|
value = (value ^ top) - top;
|
|
}
|
|
}
|
|
|
|
return value;
|
|
}
|
|
|
|
/* Determine whether the optional operand(s) should be printed. */
|
|
|
|
static bfd_boolean
|
|
skip_optional_operands (const unsigned char *opindex,
|
|
uint64_t insn, ppc_cpu_t dialect)
|
|
{
|
|
const struct powerpc_operand *operand;
|
|
int num_optional;
|
|
|
|
for (num_optional = 0; *opindex != 0; opindex++)
|
|
{
|
|
operand = &powerpc_operands[*opindex];
|
|
if ((operand->flags & PPC_OPERAND_NEXT) != 0)
|
|
return FALSE;
|
|
if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0)
|
|
{
|
|
/* Negative count is used as a flag to extract function. */
|
|
--num_optional;
|
|
if (operand_value_powerpc (operand, insn, dialect)
|
|
!= ppc_optional_operand_value (operand, insn, dialect,
|
|
num_optional))
|
|
return FALSE;
|
|
}
|
|
}
|
|
|
|
return TRUE;
|
|
}
|
|
|
|
/* Find a match for INSN in the opcode table, given machine DIALECT. */
|
|
|
|
static const struct powerpc_opcode *
|
|
lookup_powerpc (uint64_t insn, ppc_cpu_t dialect)
|
|
{
|
|
const struct powerpc_opcode *opcode, *opcode_end, *last;
|
|
unsigned long op;
|
|
|
|
/* Get the major opcode of the instruction. */
|
|
op = PPC_OP (insn);
|
|
|
|
/* Find the first match in the opcode table for this major opcode. */
|
|
opcode_end = powerpc_opcodes + powerpc_opcd_indices[op + 1];
|
|
last = NULL;
|
|
for (opcode = powerpc_opcodes + powerpc_opcd_indices[op];
|
|
opcode < opcode_end;
|
|
++opcode)
|
|
{
|
|
const unsigned char *opindex;
|
|
const struct powerpc_operand *operand;
|
|
int invalid;
|
|
|
|
if ((insn & opcode->mask) != opcode->opcode
|
|
|| ((dialect & PPC_OPCODE_ANY) == 0
|
|
&& ((opcode->flags & dialect) == 0
|
|
|| (opcode->deprecated & dialect) != 0)))
|
|
continue;
|
|
|
|
/* Check validity of operands. */
|
|
invalid = 0;
|
|
for (opindex = opcode->operands; *opindex != 0; opindex++)
|
|
{
|
|
operand = powerpc_operands + *opindex;
|
|
if (operand->extract)
|
|
(*operand->extract) (insn, dialect, &invalid);
|
|
}
|
|
if (invalid)
|
|
continue;
|
|
|
|
if ((dialect & PPC_OPCODE_RAW) == 0)
|
|
return opcode;
|
|
|
|
/* The raw machine insn is one that is not a specialization. */
|
|
if (last == NULL
|
|
|| (last->mask & ~opcode->mask) != 0)
|
|
last = opcode;
|
|
}
|
|
|
|
return last;
|
|
}
|
|
|
|
/* Find a match for INSN in the PREFIX opcode table. */
|
|
|
|
static const struct powerpc_opcode *
|
|
lookup_prefix (uint64_t insn, ppc_cpu_t dialect)
|
|
{
|
|
const struct powerpc_opcode *opcode, *opcode_end, *last;
|
|
unsigned long seg;
|
|
|
|
/* Get the opcode segment of the instruction. */
|
|
seg = PPC_PREFIX_SEG (insn);
|
|
|
|
/* Find the first match in the opcode table for this major opcode. */
|
|
opcode_end = prefix_opcodes + prefix_opcd_indices[seg + 1];
|
|
last = NULL;
|
|
for (opcode = prefix_opcodes + prefix_opcd_indices[seg];
|
|
opcode < opcode_end;
|
|
++opcode)
|
|
{
|
|
const unsigned char *opindex;
|
|
const struct powerpc_operand *operand;
|
|
int invalid;
|
|
|
|
if ((insn & opcode->mask) != opcode->opcode
|
|
|| ((dialect & PPC_OPCODE_ANY) == 0
|
|
&& ((opcode->flags & dialect) == 0
|
|
|| (opcode->deprecated & dialect) != 0)))
|
|
continue;
|
|
|
|
/* Check validity of operands. */
|
|
invalid = 0;
|
|
for (opindex = opcode->operands; *opindex != 0; opindex++)
|
|
{
|
|
operand = powerpc_operands + *opindex;
|
|
if (operand->extract)
|
|
(*operand->extract) (insn, dialect, &invalid);
|
|
}
|
|
if (invalid)
|
|
continue;
|
|
|
|
if ((dialect & PPC_OPCODE_RAW) == 0)
|
|
return opcode;
|
|
|
|
/* The raw machine insn is one that is not a specialization. */
|
|
if (last == NULL
|
|
|| (last->mask & ~opcode->mask) != 0)
|
|
last = opcode;
|
|
}
|
|
|
|
return last;
|
|
}
|
|
|
|
/* Find a match for INSN in the VLE opcode table. */
|
|
|
|
static const struct powerpc_opcode *
|
|
lookup_vle (uint64_t insn)
|
|
{
|
|
const struct powerpc_opcode *opcode;
|
|
const struct powerpc_opcode *opcode_end;
|
|
unsigned op, seg;
|
|
|
|
op = PPC_OP (insn);
|
|
if (op >= 0x20 && op <= 0x37)
|
|
{
|
|
/* This insn has a 4-bit opcode. */
|
|
op &= 0x3c;
|
|
}
|
|
seg = VLE_OP_TO_SEG (op);
|
|
|
|
/* Find the first match in the opcode table for this major opcode. */
|
|
opcode_end = vle_opcodes + vle_opcd_indices[seg + 1];
|
|
for (opcode = vle_opcodes + vle_opcd_indices[seg];
|
|
opcode < opcode_end;
|
|
++opcode)
|
|
{
|
|
uint64_t table_opcd = opcode->opcode;
|
|
uint64_t table_mask = opcode->mask;
|
|
bfd_boolean table_op_is_short = PPC_OP_SE_VLE(table_mask);
|
|
uint64_t insn2;
|
|
const unsigned char *opindex;
|
|
const struct powerpc_operand *operand;
|
|
int invalid;
|
|
|
|
insn2 = insn;
|
|
if (table_op_is_short)
|
|
insn2 >>= 16;
|
|
if ((insn2 & table_mask) != table_opcd)
|
|
continue;
|
|
|
|
/* Check validity of operands. */
|
|
invalid = 0;
|
|
for (opindex = opcode->operands; *opindex != 0; ++opindex)
|
|
{
|
|
operand = powerpc_operands + *opindex;
|
|
if (operand->extract)
|
|
(*operand->extract) (insn, (ppc_cpu_t)0, &invalid);
|
|
}
|
|
if (invalid)
|
|
continue;
|
|
|
|
return opcode;
|
|
}
|
|
|
|
return NULL;
|
|
}
|
|
|
|
/* Find a match for INSN in the SPE2 opcode table. */
|
|
|
|
static const struct powerpc_opcode *
|
|
lookup_spe2 (uint64_t insn)
|
|
{
|
|
const struct powerpc_opcode *opcode, *opcode_end;
|
|
unsigned op, xop, seg;
|
|
|
|
op = PPC_OP (insn);
|
|
if (op != 0x4)
|
|
{
|
|
/* This is not SPE2 insn.
|
|
* All SPE2 instructions have OP=4 and differs by XOP */
|
|
return NULL;
|
|
}
|
|
xop = SPE2_XOP (insn);
|
|
seg = SPE2_XOP_TO_SEG (xop);
|
|
|
|
/* Find the first match in the opcode table for this major opcode. */
|
|
opcode_end = spe2_opcodes + spe2_opcd_indices[seg + 1];
|
|
for (opcode = spe2_opcodes + spe2_opcd_indices[seg];
|
|
opcode < opcode_end;
|
|
++opcode)
|
|
{
|
|
uint64_t table_opcd = opcode->opcode;
|
|
uint64_t table_mask = opcode->mask;
|
|
uint64_t insn2;
|
|
const unsigned char *opindex;
|
|
const struct powerpc_operand *operand;
|
|
int invalid;
|
|
|
|
insn2 = insn;
|
|
if ((insn2 & table_mask) != table_opcd)
|
|
continue;
|
|
|
|
/* Check validity of operands. */
|
|
invalid = 0;
|
|
for (opindex = opcode->operands; *opindex != 0; ++opindex)
|
|
{
|
|
operand = powerpc_operands + *opindex;
|
|
if (operand->extract)
|
|
(*operand->extract) (insn, (ppc_cpu_t)0, &invalid);
|
|
}
|
|
if (invalid)
|
|
continue;
|
|
|
|
return opcode;
|
|
}
|
|
|
|
return NULL;
|
|
}
|
|
|
|
/* Print a PowerPC or POWER instruction. */
|
|
|
|
static int
|
|
print_insn_powerpc (bfd_vma memaddr,
|
|
struct disassemble_info *info,
|
|
int bigendian,
|
|
ppc_cpu_t dialect)
|
|
{
|
|
bfd_byte buffer[4];
|
|
int status;
|
|
uint64_t insn;
|
|
const struct powerpc_opcode *opcode;
|
|
int insn_length = 4; /* Assume we have a normal 4-byte instruction. */
|
|
|
|
status = (*info->read_memory_func) (memaddr, buffer, 4, info);
|
|
|
|
/* The final instruction may be a 2-byte VLE insn. */
|
|
if (status != 0 && (dialect & PPC_OPCODE_VLE) != 0)
|
|
{
|
|
/* Clear buffer so unused bytes will not have garbage in them. */
|
|
buffer[2] = buffer[3] = 0;
|
|
status = (*info->read_memory_func) (memaddr, buffer, 2, info);
|
|
insn_length = 2;
|
|
}
|
|
|
|
if (status != 0)
|
|
{
|
|
(*info->memory_error_func) (status, memaddr, info);
|
|
return -1;
|
|
}
|
|
|
|
if (bigendian)
|
|
insn = bfd_getb32 (buffer);
|
|
else
|
|
insn = bfd_getl32 (buffer);
|
|
|
|
/* Get the major opcode of the insn. */
|
|
opcode = NULL;
|
|
if ((dialect & PPC_OPCODE_POWER10) != 0
|
|
&& PPC_OP (insn) == 0x1)
|
|
{
|
|
uint64_t temp_insn, suffix;
|
|
status = (*info->read_memory_func) (memaddr + 4, buffer, 4, info);
|
|
if (status == 0)
|
|
{
|
|
if (bigendian)
|
|
suffix = bfd_getb32 (buffer);
|
|
else
|
|
suffix = bfd_getl32 (buffer);
|
|
temp_insn = (insn << 32) | suffix;
|
|
opcode = lookup_prefix (temp_insn, dialect & ~PPC_OPCODE_ANY);
|
|
if (opcode == NULL && (dialect & PPC_OPCODE_ANY) != 0)
|
|
opcode = lookup_prefix (temp_insn, dialect);
|
|
if (opcode != NULL)
|
|
{
|
|
insn = temp_insn;
|
|
insn_length = 8;
|
|
if ((info->flags & WIDE_OUTPUT) != 0)
|
|
info->bytes_per_line = 8;
|
|
}
|
|
}
|
|
}
|
|
if (opcode == NULL && (dialect & PPC_OPCODE_VLE) != 0)
|
|
{
|
|
opcode = lookup_vle (insn);
|
|
if (opcode != NULL && PPC_OP_SE_VLE (opcode->mask))
|
|
{
|
|
/* The operands will be fetched out of the 16-bit instruction. */
|
|
insn >>= 16;
|
|
insn_length = 2;
|
|
}
|
|
}
|
|
if (opcode == NULL && insn_length == 4)
|
|
{
|
|
if ((dialect & PPC_OPCODE_SPE2) != 0)
|
|
opcode = lookup_spe2 (insn);
|
|
if (opcode == NULL)
|
|
opcode = lookup_powerpc (insn, dialect & ~PPC_OPCODE_ANY);
|
|
if (opcode == NULL && (dialect & PPC_OPCODE_ANY) != 0)
|
|
opcode = lookup_powerpc (insn, dialect);
|
|
}
|
|
|
|
if (opcode != NULL)
|
|
{
|
|
const unsigned char *opindex;
|
|
const struct powerpc_operand *operand;
|
|
enum {
|
|
need_comma = 0,
|
|
need_1space = 1,
|
|
need_2spaces = 2,
|
|
need_3spaces = 3,
|
|
need_4spaces = 4,
|
|
need_5spaces = 5,
|
|
need_6spaces = 6,
|
|
need_7spaces = 7,
|
|
need_paren
|
|
} op_separator;
|
|
bfd_boolean skip_optional;
|
|
int blanks;
|
|
|
|
(*info->fprintf_func) (info->stream, "%s", opcode->name);
|
|
/* gdb fprintf_func doesn't return count printed. */
|
|
blanks = 8 - strlen (opcode->name);
|
|
if (blanks <= 0)
|
|
blanks = 1;
|
|
|
|
/* Now extract and print the operands. */
|
|
op_separator = blanks;
|
|
skip_optional = FALSE;
|
|
for (opindex = opcode->operands; *opindex != 0; opindex++)
|
|
{
|
|
int64_t value;
|
|
|
|
operand = powerpc_operands + *opindex;
|
|
|
|
/* If all of the optional operands past this one have their
|
|
default value, then don't print any of them. Except in
|
|
raw mode, print them all. */
|
|
if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0
|
|
&& (dialect & PPC_OPCODE_RAW) == 0)
|
|
{
|
|
if (!skip_optional)
|
|
skip_optional = skip_optional_operands (opindex, insn, dialect);
|
|
if (skip_optional)
|
|
continue;
|
|
}
|
|
|
|
value = operand_value_powerpc (operand, insn, dialect);
|
|
|
|
if (op_separator == need_comma)
|
|
(*info->fprintf_func) (info->stream, ",");
|
|
else if (op_separator == need_paren)
|
|
(*info->fprintf_func) (info->stream, "(");
|
|
else
|
|
(*info->fprintf_func) (info->stream, "%*s", op_separator, " ");
|
|
|
|
/* Print the operand as directed by the flags. */
|
|
if ((operand->flags & PPC_OPERAND_GPR) != 0
|
|
|| ((operand->flags & PPC_OPERAND_GPR_0) != 0 && value != 0))
|
|
(*info->fprintf_func) (info->stream, "r%" PRId64, value);
|
|
else if ((operand->flags & PPC_OPERAND_FPR) != 0)
|
|
(*info->fprintf_func) (info->stream, "f%" PRId64, value);
|
|
else if ((operand->flags & PPC_OPERAND_VR) != 0)
|
|
(*info->fprintf_func) (info->stream, "v%" PRId64, value);
|
|
else if ((operand->flags & PPC_OPERAND_VSR) != 0)
|
|
(*info->fprintf_func) (info->stream, "vs%" PRId64, value);
|
|
else if ((operand->flags & PPC_OPERAND_ACC) != 0)
|
|
(*info->fprintf_func) (info->stream, "a%" PRId64, value);
|
|
else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0)
|
|
(*info->print_address_func) (memaddr + value, info);
|
|
else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0)
|
|
(*info->print_address_func) ((bfd_vma) value & 0xffffffff, info);
|
|
else if ((operand->flags & PPC_OPERAND_FSL) != 0)
|
|
(*info->fprintf_func) (info->stream, "fsl%" PRId64, value);
|
|
else if ((operand->flags & PPC_OPERAND_FCR) != 0)
|
|
(*info->fprintf_func) (info->stream, "fcr%" PRId64, value);
|
|
else if ((operand->flags & PPC_OPERAND_UDI) != 0)
|
|
(*info->fprintf_func) (info->stream, "%" PRId64, value);
|
|
else if ((operand->flags & PPC_OPERAND_CR_REG) != 0
|
|
&& (operand->flags & PPC_OPERAND_CR_BIT) == 0
|
|
&& (((dialect & PPC_OPCODE_PPC) != 0)
|
|
|| ((dialect & PPC_OPCODE_VLE) != 0)))
|
|
(*info->fprintf_func) (info->stream, "cr%" PRId64, value);
|
|
else if ((operand->flags & PPC_OPERAND_CR_BIT) != 0
|
|
&& (operand->flags & PPC_OPERAND_CR_REG) == 0
|
|
&& (((dialect & PPC_OPCODE_PPC) != 0)
|
|
|| ((dialect & PPC_OPCODE_VLE) != 0)))
|
|
{
|
|
static const char *cbnames[4] = { "lt", "gt", "eq", "so" };
|
|
int cr;
|
|
int cc;
|
|
|
|
cr = value >> 2;
|
|
if (cr != 0)
|
|
(*info->fprintf_func) (info->stream, "4*cr%d+", cr);
|
|
cc = value & 3;
|
|
(*info->fprintf_func) (info->stream, "%s", cbnames[cc]);
|
|
}
|
|
else
|
|
(*info->fprintf_func) (info->stream, "%" PRId64, value);
|
|
|
|
if (op_separator == need_paren)
|
|
(*info->fprintf_func) (info->stream, ")");
|
|
|
|
op_separator = need_comma;
|
|
if ((operand->flags & PPC_OPERAND_PARENS) != 0)
|
|
op_separator = need_paren;
|
|
}
|
|
|
|
/* We have found and printed an instruction. */
|
|
return insn_length;
|
|
}
|
|
|
|
/* We could not find a match. */
|
|
if (insn_length == 4)
|
|
(*info->fprintf_func) (info->stream, ".long 0x%x",
|
|
(unsigned int) insn);
|
|
else
|
|
(*info->fprintf_func) (info->stream, ".word 0x%x",
|
|
(unsigned int) insn >> 16);
|
|
return insn_length;
|
|
}
|
|
|
|
const disasm_options_and_args_t *
|
|
disassembler_options_powerpc (void)
|
|
{
|
|
static disasm_options_and_args_t *opts_and_args;
|
|
|
|
if (opts_and_args == NULL)
|
|
{
|
|
size_t i, num_options = ARRAY_SIZE (ppc_opts);
|
|
disasm_options_t *opts;
|
|
|
|
opts_and_args = XNEW (disasm_options_and_args_t);
|
|
opts_and_args->args = NULL;
|
|
|
|
opts = &opts_and_args->options;
|
|
opts->name = XNEWVEC (const char *, num_options + 1);
|
|
opts->description = NULL;
|
|
opts->arg = NULL;
|
|
for (i = 0; i < num_options; i++)
|
|
opts->name[i] = ppc_opts[i].opt;
|
|
/* The array we return must be NULL terminated. */
|
|
opts->name[i] = NULL;
|
|
}
|
|
|
|
return opts_and_args;
|
|
}
|
|
|
|
void
|
|
print_ppc_disassembler_options (FILE *stream)
|
|
{
|
|
unsigned int i, col;
|
|
|
|
fprintf (stream, _("\n\
|
|
The following PPC specific disassembler options are supported for use with\n\
|
|
the -M switch:\n"));
|
|
|
|
for (col = 0, i = 0; i < ARRAY_SIZE (ppc_opts); i++)
|
|
{
|
|
col += fprintf (stream, " %s,", ppc_opts[i].opt);
|
|
if (col > 66)
|
|
{
|
|
fprintf (stream, "\n");
|
|
col = 0;
|
|
}
|
|
}
|
|
fprintf (stream, "\n");
|
|
}
|