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c3bb4211d9
Introduces instructions for the Advanced SIMD lut extension for AArch64. They are documented in the following links: * luti2: https://developer.arm.com/documentation/ddi0602/2024-03/SIMD-FP-Instructions/LUTI2--Lookup-table-read-with-2-bit-indices-?lang=en * luti4: https://developer.arm.com/documentation/ddi0602/2024-03/SIMD-FP-Instructions/LUTI4--Lookup-table-read-with-4-bit-indices-?lang=en These instructions needed definition of some new operands. We will first discuss operands for the third operand of the instructions and then discuss a vector register list operand needed for the second operand. The third operands are vectors with bit indices and without type qualifiers. They are called Em_INDEX1_14, Em_INDEX2_13, and Em_INDEX3_12 and they have 1 bit, 2 bit, and 3 bit indices respectively. For these new operands, we defined new parsing case branch. The lsb and width of these operands are the same as many existing but the convention is to give different names to fields that serve different purpose so we introduced new fields in aarch64-opc.c and aarch64-opc.h for these new operands. For the second operand of these instructions, we introduced a new operand called LVn_LUT. This represents a vector register list with stride 1. We defined new inserter and extractor for this new operand and it is encoded in FLD_Rn. We are enforcing the number of registers in the reglist using opcode flag rather than operand flag as this is what other SIMD vector register list operands are doing. The disassembly also uses opcode flag to print the correct number of registers.
152 lines
6.3 KiB
C
152 lines
6.3 KiB
C
/* aarch64-dis.h -- Header file for aarch64-dis.c and aarch64-dis-2.c.
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Copyright (C) 2012-2024 Free Software Foundation, Inc.
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Contributed by ARM Ltd.
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This file is part of the GNU opcodes library.
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This library is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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It is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; see the file COPYING3. If not,
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see <http://www.gnu.org/licenses/>. */
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#ifndef OPCODES_AARCH64_DIS_H
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#define OPCODES_AARCH64_DIS_H
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#include <stdint.h>
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#include "aarch64-opc.h"
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/* Lookup opcode WORD in the opcode table.
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In the case of multiple aarch64_opcode candidates, one of them will be
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returned; for other candidate(s), call aarch64_find_next_opcode to
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obtain. Note that aarch64_find_next_opcode finds the next
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aarch64_opcode candidate in a way as if all related aarch64_opcode
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entries were in a single-link list.
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N.B. all alias opcodes are ignored here. */
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const aarch64_opcode* aarch64_opcode_lookup (uint32_t);
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const aarch64_opcode* aarch64_find_next_opcode (const aarch64_opcode *);
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/* Given OPCODE, return its alias, e.g. given UBFM, return LSL.
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In the case of multiple alias candidates, the one of the highest priority
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(or one of several aliases of the same highest priority) will be
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returned; for the other candidate(s), call aarch64_find_next_alias_opcode
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to obtain. Note that aarch64_find_next_alias_opcode finds the next
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alias candidate in a way as if all related aliases were in a single-link
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list with priority from the highest to the least. */
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const aarch64_opcode* aarch64_find_alias_opcode (const aarch64_opcode *);
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const aarch64_opcode* aarch64_find_next_alias_opcode (const aarch64_opcode *);
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/* Switch-table-based high-level operand extractor. */
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bool
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aarch64_extract_operand (const aarch64_operand *, aarch64_opnd_info *,
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const aarch64_insn, const aarch64_inst *,
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aarch64_operand_error *);
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/* Operand extractors. */
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#define AARCH64_DECL_OPD_EXTRACTOR(x) \
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bool aarch64_##x (const aarch64_operand *, aarch64_opnd_info *, \
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const aarch64_insn, const aarch64_inst *, \
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aarch64_operand_error *)
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AARCH64_DECL_OPD_EXTRACTOR (ext_none);
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AARCH64_DECL_OPD_EXTRACTOR (ext_regno);
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AARCH64_DECL_OPD_EXTRACTOR (ext_regno_pair);
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AARCH64_DECL_OPD_EXTRACTOR (ext_regrt_sysins);
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AARCH64_DECL_OPD_EXTRACTOR (ext_reglane);
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AARCH64_DECL_OPD_EXTRACTOR (ext_reglist);
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AARCH64_DECL_OPD_EXTRACTOR (ext_ldst_reglist);
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AARCH64_DECL_OPD_EXTRACTOR (ext_ldst_reglist_r);
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AARCH64_DECL_OPD_EXTRACTOR (ext_lut_reglist);
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AARCH64_DECL_OPD_EXTRACTOR (ext_ldst_elemlist);
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AARCH64_DECL_OPD_EXTRACTOR (ext_advsimd_imm_shift);
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AARCH64_DECL_OPD_EXTRACTOR (ext_shll_imm);
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AARCH64_DECL_OPD_EXTRACTOR (ext_imm);
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AARCH64_DECL_OPD_EXTRACTOR (ext_imm_half);
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AARCH64_DECL_OPD_EXTRACTOR (ext_advsimd_imm_modified);
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AARCH64_DECL_OPD_EXTRACTOR (ext_fpimm);
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AARCH64_DECL_OPD_EXTRACTOR (ext_fbits);
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AARCH64_DECL_OPD_EXTRACTOR (ext_aimm);
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AARCH64_DECL_OPD_EXTRACTOR (ext_limm);
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AARCH64_DECL_OPD_EXTRACTOR (ext_inv_limm);
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AARCH64_DECL_OPD_EXTRACTOR (ext_ft);
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AARCH64_DECL_OPD_EXTRACTOR (ext_addr_simple);
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AARCH64_DECL_OPD_EXTRACTOR (ext_addr_offset);
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AARCH64_DECL_OPD_EXTRACTOR (ext_addr_regoff);
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AARCH64_DECL_OPD_EXTRACTOR (ext_addr_simm);
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AARCH64_DECL_OPD_EXTRACTOR (ext_addr_simm10);
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AARCH64_DECL_OPD_EXTRACTOR (ext_addr_uimm12);
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AARCH64_DECL_OPD_EXTRACTOR (ext_simd_addr_post);
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AARCH64_DECL_OPD_EXTRACTOR (ext_cond);
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AARCH64_DECL_OPD_EXTRACTOR (ext_sysreg);
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AARCH64_DECL_OPD_EXTRACTOR (ext_pstatefield);
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AARCH64_DECL_OPD_EXTRACTOR (ext_sysins_op);
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AARCH64_DECL_OPD_EXTRACTOR (ext_barrier);
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AARCH64_DECL_OPD_EXTRACTOR (ext_barrier_dsb_nxs);
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AARCH64_DECL_OPD_EXTRACTOR (ext_hint);
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AARCH64_DECL_OPD_EXTRACTOR (ext_prfop);
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AARCH64_DECL_OPD_EXTRACTOR (ext_reg_extended);
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AARCH64_DECL_OPD_EXTRACTOR (ext_reg_shifted);
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AARCH64_DECL_OPD_EXTRACTOR (ext_reg_lsl_shifted);
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AARCH64_DECL_OPD_EXTRACTOR (ext_sve_addr_ri_s4);
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AARCH64_DECL_OPD_EXTRACTOR (ext_sve_addr_ri_s4xvl);
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AARCH64_DECL_OPD_EXTRACTOR (ext_sve_addr_ri_s6xvl);
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AARCH64_DECL_OPD_EXTRACTOR (ext_sve_addr_ri_s9xvl);
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AARCH64_DECL_OPD_EXTRACTOR (ext_sve_addr_ri_u6);
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AARCH64_DECL_OPD_EXTRACTOR (ext_sve_addr_rr_lsl);
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AARCH64_DECL_OPD_EXTRACTOR (ext_sve_addr_rz_xtw);
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AARCH64_DECL_OPD_EXTRACTOR (ext_sve_addr_zi_u5);
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AARCH64_DECL_OPD_EXTRACTOR (ext_sve_addr_zz_lsl);
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AARCH64_DECL_OPD_EXTRACTOR (ext_sve_addr_zz_sxtw);
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AARCH64_DECL_OPD_EXTRACTOR (ext_sve_addr_zz_uxtw);
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AARCH64_DECL_OPD_EXTRACTOR (ext_sve_aimm);
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AARCH64_DECL_OPD_EXTRACTOR (ext_sve_aligned_reglist);
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AARCH64_DECL_OPD_EXTRACTOR (ext_sve_asimm);
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AARCH64_DECL_OPD_EXTRACTOR (ext_sve_float_half_one);
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AARCH64_DECL_OPD_EXTRACTOR (ext_sve_float_half_two);
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AARCH64_DECL_OPD_EXTRACTOR (ext_sve_float_zero_one);
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AARCH64_DECL_OPD_EXTRACTOR (ext_sve_index);
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AARCH64_DECL_OPD_EXTRACTOR (ext_sve_index_imm);
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AARCH64_DECL_OPD_EXTRACTOR (ext_sve_limm_mov);
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AARCH64_DECL_OPD_EXTRACTOR (ext_sve_quad_index);
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AARCH64_DECL_OPD_EXTRACTOR (ext_sve_reglist);
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AARCH64_DECL_OPD_EXTRACTOR (ext_sve_strided_reglist);
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AARCH64_DECL_OPD_EXTRACTOR (ext_sve_scale);
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AARCH64_DECL_OPD_EXTRACTOR (ext_sve_shlimm);
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AARCH64_DECL_OPD_EXTRACTOR (ext_sve_shrimm);
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AARCH64_DECL_OPD_EXTRACTOR (ext_sme_za_vrs1);
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AARCH64_DECL_OPD_EXTRACTOR (ext_sme_za_vrs2);
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AARCH64_DECL_OPD_EXTRACTOR (ext_sme_za_hv_tiles);
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AARCH64_DECL_OPD_EXTRACTOR (ext_sme_za_hv_tiles_range);
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AARCH64_DECL_OPD_EXTRACTOR (ext_sme_za_list);
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AARCH64_DECL_OPD_EXTRACTOR (ext_sme_za_array);
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AARCH64_DECL_OPD_EXTRACTOR (ext_sme_addr_ri_u4xvl);
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AARCH64_DECL_OPD_EXTRACTOR (ext_sme_sm_za);
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AARCH64_DECL_OPD_EXTRACTOR (ext_sme_pred_reg_with_index);
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AARCH64_DECL_OPD_EXTRACTOR (ext_imm_rotate1);
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AARCH64_DECL_OPD_EXTRACTOR (ext_imm_rotate2);
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AARCH64_DECL_OPD_EXTRACTOR (ext_x0_to_x30);
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AARCH64_DECL_OPD_EXTRACTOR (ext_simple_index);
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AARCH64_DECL_OPD_EXTRACTOR (ext_plain_shrimm);
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AARCH64_DECL_OPD_EXTRACTOR (ext_sve_reglist_zt);
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AARCH64_DECL_OPD_EXTRACTOR (ext_rcpc3_addr_opt_offset);
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AARCH64_DECL_OPD_EXTRACTOR (ext_rcpc3_addr_offset);
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#undef AARCH64_DECL_OPD_EXTRACTOR
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#endif /* OPCODES_AARCH64_DIS_H */
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