mirror of
https://sourceware.org/git/binutils-gdb.git
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1d506c26d9
This commit is the result of the following actions:
- Running gdb/copyright.py to update all of the copyright headers to
include 2024,
- Manually updating a few files the copyright.py script told me to
update, these files had copyright headers embedded within the
file,
- Regenerating gdbsupport/Makefile.in to refresh it's copyright
date,
- Using grep to find other files that still mentioned 2023. If
these files were updated last year from 2022 to 2023 then I've
updated them this year to 2024.
I'm sure I've probably missed some dates. Feel free to fix them up as
you spot them.
233 lines
6.6 KiB
C
233 lines
6.6 KiB
C
/* Lattice Mico32 exception and system call support.
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Contributed by Jon Beniston <jon@beniston.com>
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Copyright (C) 2009-2024 Free Software Foundation, Inc.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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/* This must come before any other includes. */
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#include "defs.h"
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#define WANT_CPU lm32bf
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#define WANT_CPU_LM32BF
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#include "sim-main.h"
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#include "sim-signal.h"
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#include "sim-syscall.h"
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#include "lm32-sim.h"
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#include "target-newlib-syscall.h"
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/* Handle invalid instructions. */
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SEM_PC
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sim_engine_invalid_insn (SIM_CPU * current_cpu, IADDR cia, SEM_PC pc)
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{
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SIM_DESC sd = CPU_STATE (current_cpu);
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sim_engine_halt (sd, current_cpu, NULL, cia, sim_stopped, SIM_SIGILL);
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return pc;
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}
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/* Handle divide instructions. */
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USI
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lm32bf_divu_insn (SIM_CPU * current_cpu, IADDR pc, USI r0, USI r1, USI r2)
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{
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SIM_DESC sd = CPU_STATE (current_cpu);
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/* Check for divide by zero */
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if (GET_H_GR (r1) == 0)
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{
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if (STATE_ENVIRONMENT (sd) != OPERATING_ENVIRONMENT)
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sim_engine_halt (sd, current_cpu, NULL, pc, sim_stopped, SIM_SIGFPE);
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else
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{
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/* Save PC in exception address register. */
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SET_H_GR (30, pc);
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/* Save and clear interrupt enable. */
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SET_H_CSR (LM32_CSR_IE, (GET_H_CSR (LM32_CSR_IE) & 1) << 1);
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/* Branch to divide by zero exception handler. */
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return GET_H_CSR (LM32_CSR_EBA) + LM32_EID_DIVIDE_BY_ZERO * 32;
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}
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}
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else
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{
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SET_H_GR (r2, (USI) GET_H_GR (r0) / (USI) GET_H_GR (r1));
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return pc + 4;
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}
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}
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USI
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lm32bf_modu_insn (SIM_CPU * current_cpu, IADDR pc, USI r0, USI r1, USI r2)
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{
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SIM_DESC sd = CPU_STATE (current_cpu);
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/* Check for divide by zero. */
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if (GET_H_GR (r1) == 0)
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{
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if (STATE_ENVIRONMENT (sd) != OPERATING_ENVIRONMENT)
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sim_engine_halt (sd, current_cpu, NULL, pc, sim_stopped, SIM_SIGFPE);
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else
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{
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/* Save PC in exception address register. */
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SET_H_GR (30, pc);
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/* Save and clear interrupt enable. */
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SET_H_CSR (LM32_CSR_IE, (GET_H_CSR (LM32_CSR_IE) & 1) << 1);
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/* Branch to divide by zero exception handler. */
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return GET_H_CSR (LM32_CSR_EBA) + LM32_EID_DIVIDE_BY_ZERO * 32;
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}
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}
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else
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{
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SET_H_GR (r2, (USI) GET_H_GR (r0) % (USI) GET_H_GR (r1));
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return pc + 4;
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}
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}
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/* Handle break instructions. */
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USI
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lm32bf_break_insn (SIM_CPU * current_cpu, IADDR pc)
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{
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SIM_DESC sd = CPU_STATE (current_cpu);
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/* Breakpoint. */
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if (STATE_ENVIRONMENT (sd) != OPERATING_ENVIRONMENT)
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{
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sim_engine_halt (sd, current_cpu, NULL, pc, sim_stopped, SIM_SIGTRAP);
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return pc;
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}
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else
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{
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/* Save PC in breakpoint address register. */
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SET_H_GR (31, pc);
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/* Save and clear interrupt enable. */
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SET_H_CSR (LM32_CSR_IE, (GET_H_CSR (LM32_CSR_IE) & 1) << 2);
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/* Branch to breakpoint exception handler. */
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return GET_H_CSR (LM32_CSR_DEBA) + LM32_EID_BREAKPOINT * 32;
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}
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}
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/* Handle scall instructions. */
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USI
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lm32bf_scall_insn (SIM_CPU * current_cpu, IADDR pc)
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{
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SIM_DESC sd = CPU_STATE (current_cpu);
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if ((STATE_ENVIRONMENT (sd) != OPERATING_ENVIRONMENT)
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|| (GET_H_GR (8) == TARGET_NEWLIB_SYS_exit))
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{
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/* Delegate system call to host O/S. */
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long result, result2;
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int errcode;
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/* Perform the system call. */
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sim_syscall_multi (current_cpu, GET_H_GR (8), GET_H_GR (1), GET_H_GR (2),
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GET_H_GR (3), GET_H_GR (4), &result, &result2,
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&errcode);
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/* Store the return value in the CPU's registers. */
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SET_H_GR (1, result);
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SET_H_GR (2, result2);
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SET_H_GR (3, errcode);
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/* Skip over scall instruction. */
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return pc + 4;
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}
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else
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{
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/* Save PC in exception address register. */
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SET_H_GR (30, pc);
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/* Save and clear interrupt enable */
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SET_H_CSR (LM32_CSR_IE, (GET_H_CSR (LM32_CSR_IE) & 1) << 1);
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/* Branch to system call exception handler. */
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return GET_H_CSR (LM32_CSR_EBA) + LM32_EID_SYSTEM_CALL * 32;
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}
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}
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/* Handle b instructions. */
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USI
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lm32bf_b_insn (SIM_CPU * current_cpu, USI r0, USI f_r0)
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{
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/* Restore interrupt enable. */
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if (f_r0 == 30)
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SET_H_CSR (LM32_CSR_IE, (GET_H_CSR (LM32_CSR_IE) & 2) >> 1);
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else if (f_r0 == 31)
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SET_H_CSR (LM32_CSR_IE, (GET_H_CSR (LM32_CSR_IE) & 4) >> 2);
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return r0;
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}
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/* Handle wcsr instructions. */
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void
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lm32bf_wcsr_insn (SIM_CPU * current_cpu, USI f_csr, USI r1)
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{
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/* Writing a 1 to IP CSR clears a bit, writing 0 has no effect. */
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if (f_csr == LM32_CSR_IP)
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SET_H_CSR (f_csr, GET_H_CSR (f_csr) & ~r1);
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else
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SET_H_CSR (f_csr, r1);
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}
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/* Handle signals. */
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void
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lm32_core_signal (SIM_DESC sd,
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sim_cpu * cpu,
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sim_cia cia,
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unsigned map,
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int nr_bytes,
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address_word addr,
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transfer_type transfer, sim_core_signals sig)
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{
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const char *copy = (transfer == read_transfer ? "read" : "write");
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address_word ip = CIA_ADDR (cia);
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SIM_CPU *current_cpu = cpu;
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switch (sig)
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{
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case sim_core_unmapped_signal:
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sim_io_eprintf (sd,
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"core: %d byte %s to unmapped address 0x%lx at 0x%lx\n",
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nr_bytes, copy, (unsigned long) addr,
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(unsigned long) ip);
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SET_H_GR (30, ip);
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/* Save and clear interrupt enable. */
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SET_H_CSR (LM32_CSR_IE, (GET_H_CSR (LM32_CSR_IE) & 1) << 1);
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CPU_PC_SET (cpu, GET_H_CSR (LM32_CSR_EBA) + LM32_EID_DATA_BUS_ERROR * 32);
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sim_engine_halt (sd, cpu, NULL, LM32_EID_DATA_BUS_ERROR * 32,
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sim_stopped, SIM_SIGSEGV);
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break;
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case sim_core_unaligned_signal:
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sim_io_eprintf (sd,
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"core: %d byte misaligned %s to address 0x%lx at 0x%lx\n",
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nr_bytes, copy, (unsigned long) addr,
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(unsigned long) ip);
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SET_H_GR (30, ip);
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/* Save and clear interrupt enable. */
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SET_H_CSR (LM32_CSR_IE, (GET_H_CSR (LM32_CSR_IE) & 1) << 1);
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CPU_PC_SET (cpu, GET_H_CSR (LM32_CSR_EBA) + LM32_EID_DATA_BUS_ERROR * 32);
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sim_engine_halt (sd, cpu, NULL, LM32_EID_DATA_BUS_ERROR * 32,
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sim_stopped, SIM_SIGBUS);
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break;
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default:
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sim_engine_abort (sd, cpu, cia,
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"sim_core_signal - internal error - bad switch");
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}
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}
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