mirror of
https://sourceware.org/git/binutils-gdb.git
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1d506c26d9
This commit is the result of the following actions:
- Running gdb/copyright.py to update all of the copyright headers to
include 2024,
- Manually updating a few files the copyright.py script told me to
update, these files had copyright headers embedded within the
file,
- Regenerating gdbsupport/Makefile.in to refresh it's copyright
date,
- Using grep to find other files that still mentioned 2023. If
these files were updated last year from 2022 to 2023 then I've
updated them this year to 2024.
I'm sure I've probably missed some dates. Feel free to fix them up as
you spot them.
422 lines
11 KiB
C
422 lines
11 KiB
C
/* CRIS base simulator support code
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Copyright (C) 2004-2024 Free Software Foundation, Inc.
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Contributed by Axis Communications.
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This file is part of the GNU simulators.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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/* The infrastructure is based on that of i960.c. */
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/* This must come before any other includes. */
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#include "defs.h"
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#define WANT_CPU
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#include "sim-main.h"
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#include "cgen-mem.h"
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#include "cgen-ops.h"
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#include <stdlib.h>
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#define MY(f) XCONCAT3(crisv,BASENUM,f)
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/* Dispatcher for break insn. */
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USI
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MY (f_break_handler) (SIM_CPU *cpu, USI breaknum, USI pc)
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{
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SIM_DESC sd = CPU_STATE (cpu);
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USI ret = pc + 2;
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MY (f_h_pc_set) (cpu, ret);
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/* FIXME: Error out if IBR or ERP set. */
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switch (breaknum)
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{
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case 13:
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MY (f_h_gr_set (cpu, 10,
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cris_break_13_handler (cpu,
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MY (f_h_gr_get (cpu, 9)),
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MY (f_h_gr_get (cpu, 10)),
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MY (f_h_gr_get (cpu, 11)),
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MY (f_h_gr_get (cpu, 12)),
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MY (f_h_gr_get (cpu, 13)),
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MY (f_h_sr_get (cpu, 7)),
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MY (f_h_sr_get (cpu, 11)),
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pc)));
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break;
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case 14:
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sim_io_printf (sd, "%x\n", MY (f_h_gr_get (cpu, 3)));
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break;
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case 15:
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/* Re-use the Linux exit call. */
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cris_break_13_handler (cpu, /* TARGET_SYS_exit */ 1, 0,
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0, 0, 0, 0, 0, pc);
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/* This shouldn't be reached, but we can't mark break 13 as noreturn
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since there are some calls which should return. */
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ATTRIBUTE_FALLTHROUGH;
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default:
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abort ();
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}
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return MY (f_h_pc_get) (cpu);
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}
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/* Accessor function for simulator internal use.
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Note the contents of BUF are in target byte order. */
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int
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MY (f_fetch_register) (SIM_CPU *current_cpu, int rn, void *buf,
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int len ATTRIBUTE_UNUSED)
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{
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SETTSI (buf, XCONCAT3(crisv,BASENUM,f_h_gr_get) (current_cpu, rn));
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return -1;
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}
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/* Accessor function for simulator internal use.
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Note the contents of BUF are in target byte order. */
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int
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MY (f_store_register) (SIM_CPU *current_cpu, int rn, const void *buf,
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int len ATTRIBUTE_UNUSED)
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{
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XCONCAT3(crisv,BASENUM,f_h_gr_set) (current_cpu, rn, GETTSI (buf));
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return -1;
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}
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#if WITH_PROFILE_MODEL_P
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/* FIXME: Some of these should be inline or macros. Later. */
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/* Initialize cycle counting for an insn.
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FIRST_P is non-zero if this is the first insn in a set of parallel
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insns. */
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void
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MY (f_model_insn_before) (SIM_CPU *current_cpu, int first_p ATTRIBUTE_UNUSED)
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{
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/* To give the impression that we actually know what PC is, we have to
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dump register contents *before* the *next* insn, not after the
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*previous* insn. Uhh... */
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/* FIXME: Move this to separate, overridable function. */
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if ((CPU_CRIS_MISC_PROFILE (current_cpu)->flags
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& FLAG_CRIS_MISC_PROFILE_XSIM_TRACE)
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#ifdef GET_H_INSN_PREFIXED_P
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/* For versions with prefixed insns, trace the combination as
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one insn. */
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&& !GET_H_INSN_PREFIXED_P ()
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#endif
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&& 1)
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{
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int i;
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char flags[7];
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uint64_t cycle_count;
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SIM_DESC sd = CPU_STATE (current_cpu);
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cris_trace_printf (sd, current_cpu, "%lx ",
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0xffffffffUL & (unsigned long) (CPU (h_pc)));
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for (i = 0; i < 15; i++)
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cris_trace_printf (sd, current_cpu, "%lx ",
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0xffffffffUL
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& (unsigned long) (XCONCAT3(crisv,BASENUM,
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f_h_gr_get) (current_cpu,
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i)));
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flags[0] = GET_H_IBIT () != 0 ? 'I' : 'i';
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flags[1] = GET_H_XBIT () != 0 ? 'X' : 'x';
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flags[2] = GET_H_NBIT () != 0 ? 'N' : 'n';
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flags[3] = GET_H_ZBIT () != 0 ? 'Z' : 'z';
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flags[4] = GET_H_VBIT () != 0 ? 'V' : 'v';
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flags[5] = GET_H_CBIT () != 0 ? 'C' : 'c';
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flags[6] = 0;
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/* For anything else than basic tracing we'd add stall cycles for
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e.g. unaligned accesses. FIXME: add --cris-trace=x options to
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match --cris-cycles=x. */
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cycle_count
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= (CPU_CRIS_MISC_PROFILE (current_cpu)->basic_cycle_count
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- CPU_CRIS_PREV_MISC_PROFILE (current_cpu)->basic_cycle_count);
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/* Emit ACR after flags and cycle count for this insn. */
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if (BASENUM == 32)
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cris_trace_printf (sd, current_cpu, "%s %d %lx\n", flags,
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(int) cycle_count,
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0xffffffffUL
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& (unsigned long) (XCONCAT3(crisv,BASENUM,
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f_h_gr_get) (current_cpu,
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15)));
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else
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cris_trace_printf (sd, current_cpu, "%s %d\n", flags,
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(int) cycle_count);
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CPU_CRIS_PREV_MISC_PROFILE (current_cpu)[0]
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= CPU_CRIS_MISC_PROFILE (current_cpu)[0];
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}
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}
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/* Record the cycles computed for an insn.
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LAST_P is non-zero if this is the last insn in a set of parallel insns,
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and we update the total cycle count.
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CYCLES is the cycle count of the insn. */
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void
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MY (f_model_insn_after) (SIM_CPU *current_cpu, int last_p ATTRIBUTE_UNUSED,
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int cycles)
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{
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PROFILE_DATA *p = CPU_PROFILE_DATA (current_cpu);
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PROFILE_MODEL_TOTAL_CYCLES (p) += cycles;
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CPU_CRIS_MISC_PROFILE (current_cpu)->basic_cycle_count += cycles;
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PROFILE_MODEL_CUR_INSN_CYCLES (p) = cycles;
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#if WITH_HW
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/* For some reason, we don't get to the sim_events_tick call in
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cgen-run.c:engine_run_1. Besides, more than one cycle has
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passed, so we want sim_events_tickn anyway. The "events we want
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to process" is usually to initiate an interrupt, but might also
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be other events. We can't do the former until the main loop is
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at point where it accepts changing the PC without internal
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inconsistency, so just set a flag and wait. */
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if (sim_events_tickn (CPU_STATE (current_cpu), cycles))
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STATE_EVENTS (CPU_STATE (current_cpu))->work_pending = 1;
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#endif
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}
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#if 0
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/* Initialize cycle counting for an insn.
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FIRST_P is non-zero if this is the first insn in a set of parallel
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insns. */
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void
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MY (f_model_init_insn_cycles) (SIM_CPU *current_cpu ATTRIBUTE_UNUSED,
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int first_p ATTRIBUTE_UNUSED)
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{
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abort ();
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}
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/* Record the cycles computed for an insn.
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LAST_P is non-zero if this is the last insn in a set of parallel insns,
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and we update the total cycle count. */
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void
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MY (f_model_update_insn_cycles) (SIM_CPU *current_cpu ATTRIBUTE_UNUSED,
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int last_p ATTRIBUTE_UNUSED)
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{
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abort ();
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}
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void
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MY (f_model_record_cycles) (SIM_CPU *current_cpu, unsigned long cycles)
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{
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abort ();
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}
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void
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MY (f_model_mark_get_h_gr) (SIM_CPU *current_cpu, ARGBUF *abuf)
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{
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abort ();
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}
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void
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MY (f_model_mark_set_h_gr) (SIM_CPU *current_cpu, ARGBUF *abuf)
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{
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abort ();
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}
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#endif
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/* Set the thread register contents. */
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static void
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MY (set_target_thread_data) (SIM_CPU *current_cpu, USI val)
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{
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(CPU (XCONCAT2 (h_sr_v, BASENUM) [CRIS_TLS_REGISTER])) = val;
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}
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/* Create the context for a thread. */
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static void *
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MY (make_thread_cpu_data) (SIM_CPU *current_cpu, void *context)
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{
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struct cris_sim_cpu *cris_cpu = CRIS_SIM_CPU (current_cpu);
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void *info = xmalloc (cris_cpu->thread_cpu_data_size);
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if (context != NULL)
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memcpy (info, context, cris_cpu->thread_cpu_data_size);
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else
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memset (info, 0, cris_cpu->thread_cpu_data_size),abort();
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return info;
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}
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/* Placate -Wmissing-prototypes when mloop.in isn't used. */
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void MY (f_specific_init) (SIM_CPU *current_cpu);
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/* Hook function for per-cpu simulator initialization. */
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void
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MY (f_specific_init) (SIM_CPU *current_cpu)
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{
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struct cris_sim_cpu *cris_cpu = CRIS_SIM_CPU (current_cpu);
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cris_cpu->make_thread_cpu_data = MY (make_thread_cpu_data);
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cris_cpu->thread_cpu_data_size = sizeof (cris_cpu->cpu_data);
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cris_cpu->set_target_thread_data = MY (set_target_thread_data);
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#if WITH_HW
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cris_cpu->deliver_interrupt = MY (deliver_interrupt);
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#endif
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}
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/* Placate -Wmissing-prototypes when mloop.in isn't used. */
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int MY (XCONCAT3 (f_model_crisv,BASENUM, _u_stall))
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(SIM_CPU *current_cpu ATTRIBUTE_UNUSED,
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const IDESC *idesc,
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int unit_num,
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int referenced ATTRIBUTE_UNUSED);
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/* Model function for arbitrary single stall cycles. */
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int
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MY (XCONCAT3 (f_model_crisv,BASENUM,
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_u_stall)) (SIM_CPU *current_cpu ATTRIBUTE_UNUSED,
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const IDESC *idesc,
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int unit_num,
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int referenced ATTRIBUTE_UNUSED)
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{
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return idesc->timing->units[unit_num].done;
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}
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#ifndef SPECIFIC_U_SKIP4_FN
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/* Model function for u-skip4 unit. */
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int
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MY (XCONCAT3 (f_model_crisv,BASENUM,
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_u_skip4)) (SIM_CPU *current_cpu,
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const IDESC *idesc,
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int unit_num,
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int referenced ATTRIBUTE_UNUSED)
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{
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/* Handle PC not being updated with pbb. FIXME: What if not pbb? */
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CPU (h_pc) += 4;
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return idesc->timing->units[unit_num].done;
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}
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#endif
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#ifndef SPECIFIC_U_EXEC_FN
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/* Model function for u-exec unit. */
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int
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MY (XCONCAT3 (f_model_crisv,BASENUM,
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_u_exec)) (SIM_CPU *current_cpu,
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const IDESC *idesc,
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int unit_num, int referenced ATTRIBUTE_UNUSED)
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{
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/* Handle PC not being updated with pbb. FIXME: What if not pbb? */
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CPU (h_pc) += 2;
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return idesc->timing->units[unit_num].done;
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}
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#endif
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#ifndef SPECIFIC_U_MEM_FN
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/* Model function for u-mem unit. */
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int
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MY (XCONCAT3 (f_model_crisv,BASENUM,
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_u_mem)) (SIM_CPU *current_cpu ATTRIBUTE_UNUSED,
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const IDESC *idesc,
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int unit_num,
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int referenced ATTRIBUTE_UNUSED)
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{
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return idesc->timing->units[unit_num].done;
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}
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#endif
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#ifndef SPECIFIC_U_CONST16_FN
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/* Model function for u-const16 unit. */
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int
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MY (XCONCAT3 (f_model_crisv,BASENUM,
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_u_const16)) (SIM_CPU *current_cpu,
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const IDESC *idesc,
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int unit_num,
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int referenced ATTRIBUTE_UNUSED)
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{
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CPU (h_pc) += 2;
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return idesc->timing->units[unit_num].done;
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}
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#endif /* SPECIFIC_U_CONST16_FN */
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#ifndef SPECIFIC_U_CONST32_FN
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/* This will be incorrect for early models, where a dword always take
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two cycles. */
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#define CRIS_MODEL_MASK_PC_STALL 2
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/* Model function for u-const32 unit. */
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int
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MY (XCONCAT3 (f_model_crisv,BASENUM,
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_u_const32)) (SIM_CPU *current_cpu,
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const IDESC *idesc,
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int unit_num,
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int referenced ATTRIBUTE_UNUSED)
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{
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int unaligned_extra
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= (((CPU (h_pc) + 2) & CRIS_MODEL_MASK_PC_STALL)
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== CRIS_MODEL_MASK_PC_STALL);
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/* Handle PC not being updated with pbb. FIXME: What if not pbb? */
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CPU_CRIS_MISC_PROFILE (current_cpu)->unaligned_mem_dword_count
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+= unaligned_extra;
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CPU (h_pc) += 4;
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return idesc->timing->units[unit_num].done;
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}
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#endif /* SPECIFIC_U_CONST32_FN */
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#ifndef SPECIFIC_U_MOVEM_FN
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/* Model function for u-movem unit. */
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int
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MY (XCONCAT3 (f_model_crisv,BASENUM,
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_u_movem)) (SIM_CPU *current_cpu ATTRIBUTE_UNUSED,
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const IDESC *idesc ATTRIBUTE_UNUSED,
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int unit_num ATTRIBUTE_UNUSED,
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int referenced ATTRIBUTE_UNUSED,
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INT limreg)
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{
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/* FIXME: Add cycles for misalignment. */
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if (limreg == -1)
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abort ();
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/* We don't record movem move cycles in movemsrc_stall_count since
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those cycles have historically been handled as ordinary cycles. */
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return limreg + 1;
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}
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#endif /* SPECIFIC_U_MOVEM_FN */
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#endif /* WITH_PROFILE_MODEL_P */
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