binutils-gdb/sim/v850
Jeff Law 477904ca75 Fix for v850e divq instruction
This is the last of the correctness fixes I've been carrying around for the
v850.

Like the other recent fixes, this is another case where we haven't been as
careful as we should WRT host vs target types.   For the divq instruction
both operands are 32 bit types.  Yet in the simulator code we convert them
from unsigned int to signed long by assignment.  So 0xfffffffb (aka -5)
turns into 4294967291 and naturally that changes the result of our division.

The fix is simple, insert a cast to int32_t to force interpretation as a
signed value.

Testcase for the simulator is included.  It has a trivial dependency on the
bins patch.
2022-04-06 11:10:40 -04:00
..
aclocal.m4 sim: unify reserved instruction bits settings 2021-07-01 20:53:00 -04:00
ChangeLog-2021 sim: rename ChangeLog files to ChangeLog-2021 2021-08-17 20:27:36 -04:00
configure sim: gdbinit: hoist setup to common code 2022-02-21 13:57:33 -05:00
configure.ac sim: unify reserved instruction bits settings 2021-07-01 20:53:00 -04:00
interp.c sim: v850: migrate to standard uintXX_t types 2022-01-06 01:17:37 -05:00
local.mk Automatic Copyright Year update after running gdb/copyright.py 2022-01-01 19:13:23 +04:00
Makefile.in Automatic Copyright Year update after running gdb/copyright.py 2022-01-01 19:13:23 +04:00
sim-main.h sim: v850: migrate to standard uintXX_t types 2022-01-06 01:17:37 -05:00
simops.c Fix for v850e divq instruction 2022-04-06 11:10:40 -04:00
simops.h sim: v850: migrate to standard uintXX_t types 2022-01-06 01:17:37 -05:00
v850_sim.h remove PARAMS from sim 2014-01-07 09:17:05 -07:00
v850-dc Fixes problems building the V850 simulator introduced with the previous delta. 2015-02-27 09:53:03 +00:00
v850.igen sim: v850: migrate to standard uintXX_t types 2022-01-06 01:17:37 -05:00