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d87bef3a7b
The newer update-copyright.py fixes file encoding too, removing cr/lf on binutils/bfdtest2.c and ld/testsuite/ld-cygwin/exe-export.exp, and embedded cr in binutils/testsuite/binutils-all/ar.exp string match.
236 lines
8.0 KiB
C
236 lines
8.0 KiB
C
/* Nios II opcode list for GAS, the GNU assembler.
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Copyright (C) 2012-2023 Free Software Foundation, Inc.
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Contributed by Nigel Gray (ngray@altera.com).
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Contributed by Mentor Graphics, Inc.
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This file is part of the GNU opcodes library.
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GAS/GDB is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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GAS/GDB is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with GAS or GDB; see the file COPYING3. If not, write to
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the Free Software Foundation, 51 Franklin Street - Fifth Floor,
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Boston, MA 02110-1301, USA. */
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#ifndef _NIOS2_H_
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#define _NIOS2_H_
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#include "bfd.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/****************************************************************************
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* This file contains structures, bit masks and shift counts used
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* by the GNU toolchain to define the Nios II instruction set and
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* access various opcode fields.
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****************************************************************************/
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/* Instruction encoding formats. */
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enum iw_format_type {
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/* R1 formats. */
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iw_i_type,
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iw_r_type,
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iw_j_type,
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iw_custom_type,
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/* 32-bit R2 formats. */
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iw_L26_type,
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iw_F2I16_type,
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iw_F2X4I12_type,
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iw_F1X4I12_type,
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iw_F1X4L17_type,
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iw_F3X6L5_type,
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iw_F2X6L10_type,
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iw_F3X6_type,
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iw_F3X8_type,
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/* 16-bit R2 formats. */
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iw_I10_type,
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iw_T1I7_type,
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iw_T2I4_type,
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iw_T1X1I6_type,
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iw_X1I7_type,
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iw_L5I4X1_type,
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iw_T2X1L3_type,
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iw_T2X1I3_type,
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iw_T3X1_type,
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iw_T2X3_type,
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iw_F1X1_type,
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iw_X2L5_type,
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iw_F1I5_type,
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iw_F2_type
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};
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/* Identify different overflow situations for error messages. */
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enum overflow_type
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{
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call_target_overflow = 0,
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branch_target_overflow,
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address_offset_overflow,
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signed_immed16_overflow,
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unsigned_immed16_overflow,
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unsigned_immed5_overflow,
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signed_immed12_overflow,
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custom_opcode_overflow,
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enumeration_overflow,
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no_overflow
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};
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/* This structure holds information for a particular instruction.
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The args field is a string describing the operands. The following
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letters can appear in the args:
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c - a 5-bit control register index
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d - a 5-bit destination register index
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s - a 5-bit left source register index
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t - a 5-bit right source register index
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D - a 3-bit encoded destination register
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S - a 3-bit encoded left source register
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T - a 3-bit encoded right source register
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i - a 16-bit signed immediate
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j - a 5-bit unsigned immediate
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k - a (second) 5-bit unsigned immediate
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l - a 8-bit custom instruction constant
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m - a 26-bit unsigned immediate
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o - a 16-bit signed pc-relative offset
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u - a 16-bit unsigned immediate
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I - a 12-bit signed immediate
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M - a 6-bit unsigned immediate
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N - a 6-bit unsigned immediate with 2-bit shift
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O - a 10-bit signed pc-relative offset with 1-bit shift
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P - a 7-bit signed pc-relative offset with 1-bit shift
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U - a 7-bit unsigned immediate with 2-bit shift
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V - a 5-bit unsigned immediate with 2-bit shift
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W - a 4-bit unsigned immediate with 2-bit shift
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X - a 4-bit unsigned immediate with 1-bit shift
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Y - a 4-bit unsigned immediate
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e - an immediate coded as an enumeration for addi.n/subi.n
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f - an immediate coded as an enumeration for slli.n/srli.n
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g - an immediate coded as an enumeration for andi.n
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h - an immediate coded as an enumeration for movi.n
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R - a reglist for ldwm/stwm or push.n/pop.n
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B - a base register specifier and option list for ldwm/stwm
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Literal ',', '(', and ')' characters may also appear in the args as
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delimiters.
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Note that the args describe the semantics and assembly-language syntax
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of the operands, not their encoding into the instruction word.
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The pinfo field is INSN_MACRO for a macro. Otherwise, it is a collection
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of bits describing the instruction, notably any relevant hazard
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information.
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When assembling, the match field contains the opcode template, which
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is modified by the arguments to produce the actual opcode
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that is emitted. If pinfo is INSN_MACRO, then this is 0.
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If pinfo is INSN_MACRO, the mask field stores the macro identifier.
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Otherwise this is a bit mask for the relevant portions of the opcode
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when disassembling. If the actual opcode anded with the match field
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equals the opcode field, then we have found the correct instruction. */
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struct nios2_opcode
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{
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const char *name; /* The name of the instruction. */
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const char *args; /* A string describing the arguments for this
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instruction. */
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const char *args_test; /* Like args, but with an extra argument for
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the expected opcode. */
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unsigned long num_args; /* The number of arguments the instruction
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takes. */
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unsigned size; /* Size in bytes of the instruction. */
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enum iw_format_type format; /* Instruction format. */
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unsigned long match; /* The basic opcode for the instruction. */
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unsigned long mask; /* Mask for the opcode field of the
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instruction. */
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unsigned long pinfo; /* Is this a real instruction or instruction
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macro? */
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enum overflow_type overflow_msg; /* Used to generate informative
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message when fixup overflows. */
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};
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/* This value is used in the nios2_opcode.pinfo field to indicate that the
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instruction is a macro or pseudo-op. This requires special treatment by
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the assembler, and is used by the disassembler to determine whether to
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check for a nop. */
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#define NIOS2_INSN_MACRO 0x80000000
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#define NIOS2_INSN_MACRO_MOV 0x80000001
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#define NIOS2_INSN_MACRO_MOVI 0x80000002
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#define NIOS2_INSN_MACRO_MOVIA 0x80000004
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#define NIOS2_INSN_RELAXABLE 0x40000000
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#define NIOS2_INSN_UBRANCH 0x00000010
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#define NIOS2_INSN_CBRANCH 0x00000020
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#define NIOS2_INSN_CALL 0x00000040
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#define NIOS2_INSN_OPTARG 0x00000080
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/* Register attributes. */
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#define REG_NORMAL (1<<0) /* Normal registers. */
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#define REG_CONTROL (1<<1) /* Control registers. */
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#define REG_COPROCESSOR (1<<2) /* For custom instructions. */
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#define REG_3BIT (1<<3) /* For R2 CDX instructions. */
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#define REG_LDWM (1<<4) /* For R2 ldwm/stwm. */
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#define REG_POP (1<<5) /* For R2 pop.n/push.n. */
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struct nios2_reg
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{
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const char *name;
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const int index;
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unsigned long regtype;
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};
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/* Pull in the instruction field accessors, opcodes, and masks. */
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#include "nios2r1.h"
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#include "nios2r2.h"
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/* These are the data structures used to hold the instruction information. */
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extern const struct nios2_opcode nios2_r1_opcodes[];
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extern const int nios2_num_r1_opcodes;
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extern const struct nios2_opcode nios2_r2_opcodes[];
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extern const int nios2_num_r2_opcodes;
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extern struct nios2_opcode *nios2_opcodes;
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extern int nios2_num_opcodes;
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/* These are the data structures used to hold the register information. */
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extern const struct nios2_reg nios2_builtin_regs[];
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extern struct nios2_reg *nios2_regs;
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extern const int nios2_num_builtin_regs;
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extern int nios2_num_regs;
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/* Return the opcode descriptor for a single instruction. */
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extern const struct nios2_opcode *
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nios2_find_opcode_hash (unsigned long, unsigned long);
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/* Lookup tables for R2 immediate decodings. */
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extern unsigned int nios2_r2_asi_n_mappings[];
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extern const int nios2_num_r2_asi_n_mappings;
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extern unsigned int nios2_r2_shi_n_mappings[];
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extern const int nios2_num_r2_shi_n_mappings;
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extern unsigned int nios2_r2_andi_n_mappings[];
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extern const int nios2_num_r2_andi_n_mappings;
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/* Lookup table for 3-bit register decodings. */
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extern int nios2_r2_reg3_mappings[];
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extern const int nios2_num_r2_reg3_mappings;
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/* Lookup table for REG_RANGE value list decodings. */
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extern unsigned long nios2_r2_reg_range_mappings[];
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extern const int nios2_num_r2_reg_range_mappings;
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#ifdef __cplusplus
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}
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#endif
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#endif /* _NIOS2_H */
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