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213516ef31
This commit is the result of running the gdb/copyright.py script, which automated the update of the copyright year range for all source files managed by the GDB project to be updated to include year 2023.
449 lines
11 KiB
C++
449 lines
11 KiB
C++
/* Target dependent code for GDB on TI C6x systems.
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Copyright (C) 2010-2023 Free Software Foundation, Inc.
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Contributed by Andrew Jenner <andrew@codesourcery.com>
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Contributed by Yao Qi <yao@codesourcery.com>
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#include "server.h"
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#include "linux-low.h"
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#include "arch/tic6x.h"
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#include "tdesc.h"
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#include "nat/gdb_ptrace.h"
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#include <endian.h>
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#include "gdb_proc_service.h"
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#ifndef PTRACE_GET_THREAD_AREA
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#define PTRACE_GET_THREAD_AREA 25
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#endif
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/* There are at most 69 registers accessible in ptrace. */
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#define TIC6X_NUM_REGS 69
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#include <asm/ptrace.h>
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/* Linux target op definitions for the TI C6x architecture. */
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class tic6x_target : public linux_process_target
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{
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public:
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const regs_info *get_regs_info () override;
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const gdb_byte *sw_breakpoint_from_kind (int kind, int *size) override;
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protected:
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void low_arch_setup () override;
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bool low_cannot_fetch_register (int regno) override;
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bool low_cannot_store_register (int regno) override;
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bool low_supports_breakpoints () override;
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CORE_ADDR low_get_pc (regcache *regcache) override;
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void low_set_pc (regcache *regcache, CORE_ADDR newpc) override;
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bool low_breakpoint_at (CORE_ADDR pc) override;
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};
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/* The singleton target ops object. */
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static tic6x_target the_tic6x_target;
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/* Defined in auto-generated file tic6x-c64xp-linux.c. */
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void init_registers_tic6x_c64xp_linux (void);
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extern const struct target_desc *tdesc_tic6x_c64xp_linux;
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/* Defined in auto-generated file tic6x-c64x-linux.c. */
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void init_registers_tic6x_c64x_linux (void);
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extern const struct target_desc *tdesc_tic6x_c64x_linux;
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/* Defined in auto-generated file tic62x-c6xp-linux.c. */
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void init_registers_tic6x_c62x_linux (void);
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extern const struct target_desc *tdesc_tic6x_c62x_linux;
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union tic6x_register
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{
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unsigned char buf[4];
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int reg32;
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};
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/* Return the ptrace ``address'' of register REGNO. */
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#if __BYTE_ORDER == __BIG_ENDIAN
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static int tic6x_regmap_c64xp[] = {
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/* A0 - A15 */
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53, 52, 55, 54, 57, 56, 59, 58,
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61, 60, 63, 62, 65, 64, 67, 66,
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/* B0 - B15 */
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23, 22, 25, 24, 27, 26, 29, 28,
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31, 30, 33, 32, 35, 34, 69, 68,
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/* CSR PC */
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5, 4,
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/* A16 - A31 */
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37, 36, 39, 38, 41, 40, 43, 42,
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45, 44, 47, 46, 49, 48, 51, 50,
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/* B16 - B31 */
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7, 6, 9, 8, 11, 10, 13, 12,
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15, 14, 17, 16, 19, 18, 21, 20,
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/* TSR, ILC, RILC */
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1, 2, 3
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};
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static int tic6x_regmap_c64x[] = {
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/* A0 - A15 */
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51, 50, 53, 52, 55, 54, 57, 56,
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59, 58, 61, 60, 63, 62, 65, 64,
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/* B0 - B15 */
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21, 20, 23, 22, 25, 24, 27, 26,
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29, 28, 31, 30, 33, 32, 67, 66,
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/* CSR PC */
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3, 2,
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/* A16 - A31 */
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35, 34, 37, 36, 39, 38, 41, 40,
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43, 42, 45, 44, 47, 46, 49, 48,
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/* B16 - B31 */
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5, 4, 7, 6, 9, 8, 11, 10,
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13, 12, 15, 14, 17, 16, 19, 18,
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-1, -1, -1
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};
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static int tic6x_regmap_c62x[] = {
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/* A0 - A15 */
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19, 18, 21, 20, 23, 22, 25, 24,
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27, 26, 29, 28, 31, 30, 33, 32,
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/* B0 - B15 */
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5, 4, 7, 6, 9, 8, 11, 10,
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13, 12, 15, 14, 17, 16, 35, 34,
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/* CSR, PC */
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3, 2,
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-1, -1, -1, -1, -1, -1, -1, -1,
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-1, -1, -1, -1, -1, -1, -1, -1,
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-1, -1, -1, -1, -1, -1, -1, -1,
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-1, -1, -1, -1, -1, -1, -1, -1,
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-1, -1, -1
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};
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#else
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static int tic6x_regmap_c64xp[] = {
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/* A0 - A15 */
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52, 53, 54, 55, 56, 57, 58, 59,
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60, 61, 62, 63, 64, 65, 66, 67,
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/* B0 - B15 */
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22, 23, 24, 25, 26, 27, 28, 29,
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30, 31, 32, 33, 34, 35, 68, 69,
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/* CSR PC */
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4, 5,
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/* A16 - A31 */
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36, 37, 38, 39, 40, 41, 42, 43,
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44, 45, 46, 47, 48, 49, 50, 51,
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/* B16 -B31 */
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6, 7, 8, 9, 10, 11, 12, 13,
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14, 15, 16, 17, 18, 19, 20, 31,
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/* TSR, ILC, RILC */
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0, 3, 2
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};
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static int tic6x_regmap_c64x[] = {
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/* A0 - A15 */
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50, 51, 52, 53, 54, 55, 56, 57,
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58, 59, 60, 61, 62, 63, 64, 65,
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/* B0 - B15 */
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20, 21, 22, 23, 24, 25, 26, 27,
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28, 29, 30, 31, 32, 33, 66, 67,
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/* CSR PC */
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2, 3,
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/* A16 - A31 */
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34, 35, 36, 37, 38, 39, 40, 41,
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42, 43, 44, 45, 46, 47, 48, 49,
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/* B16 - B31 */
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4, 5, 6, 7, 8, 9, 10, 11,
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12, 13, 14, 15, 16, 17, 18, 19,
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-1, -1, -1
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};
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static int tic6x_regmap_c62x[] = {
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/* A0 - A15 */
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18, 19, 20, 21, 22, 23, 24, 25,
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26, 27, 28, 29, 30, 31, 32, 33,
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/* B0 - B15 */
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4, 5, 6, 7, 8, 9, 10, 11,
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12, 13, 14, 15, 16, 17, 34, 35,
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/* CSR PC */
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2, 3,
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-1, -1, -1, -1, -1, -1, -1, -1,
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-1, -1, -1, -1, -1, -1, -1, -1,
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-1, -1, -1, -1, -1, -1, -1, -1,
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-1, -1, -1, -1, -1, -1, -1, -1,
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-1, -1, -1
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};
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#endif
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static int *tic6x_regmap;
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static unsigned int tic6x_breakpoint;
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#define tic6x_breakpoint_len 4
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/* Implementation of target ops method "sw_breakpoint_from_kind". */
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const gdb_byte *
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tic6x_target::sw_breakpoint_from_kind (int kind, int *size)
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{
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*size = tic6x_breakpoint_len;
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return (const gdb_byte *) &tic6x_breakpoint;
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}
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static struct usrregs_info tic6x_usrregs_info =
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{
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TIC6X_NUM_REGS,
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NULL, /* Set in tic6x_read_description. */
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};
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static const struct target_desc *
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tic6x_read_description (enum c6x_feature feature)
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{
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static target_desc *tdescs[C6X_LAST] = { };
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struct target_desc **tdesc = &tdescs[feature];
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if (*tdesc == NULL)
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{
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*tdesc = tic6x_create_target_description (feature);
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static const char *expedite_regs[] = { "A15", "PC", NULL };
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init_target_desc (*tdesc, expedite_regs);
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}
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return *tdesc;
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}
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bool
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tic6x_target::low_cannot_fetch_register (int regno)
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{
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return (tic6x_regmap[regno] == -1);
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}
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bool
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tic6x_target::low_cannot_store_register (int regno)
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{
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return (tic6x_regmap[regno] == -1);
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}
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bool
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tic6x_target::low_supports_breakpoints ()
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{
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return true;
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}
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CORE_ADDR
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tic6x_target::low_get_pc (regcache *regcache)
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{
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union tic6x_register pc;
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collect_register_by_name (regcache, "PC", pc.buf);
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return pc.reg32;
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}
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void
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tic6x_target::low_set_pc (regcache *regcache, CORE_ADDR pc)
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{
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union tic6x_register newpc;
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newpc.reg32 = pc;
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supply_register_by_name (regcache, "PC", newpc.buf);
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}
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bool
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tic6x_target::low_breakpoint_at (CORE_ADDR where)
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{
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unsigned int insn;
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read_memory (where, (unsigned char *) &insn, 4);
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if (insn == tic6x_breakpoint)
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return true;
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/* If necessary, recognize more trap instructions here. GDB only uses the
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one. */
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return false;
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}
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/* Fetch the thread-local storage pointer for libthread_db. */
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ps_err_e
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ps_get_thread_area (struct ps_prochandle *ph,
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lwpid_t lwpid, int idx, void **base)
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{
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if (ptrace (PTRACE_GET_THREAD_AREA, lwpid, NULL, base) != 0)
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return PS_ERR;
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/* IDX is the bias from the thread pointer to the beginning of the
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thread descriptor. It has to be subtracted due to implementation
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quirks in libthread_db. */
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*base = (void *) ((char *) *base - idx);
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return PS_OK;
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}
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static void
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tic6x_collect_register (struct regcache *regcache, int regno,
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union tic6x_register *reg)
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{
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union tic6x_register tmp_reg;
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collect_register (regcache, regno, &tmp_reg.reg32);
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reg->reg32 = tmp_reg.reg32;
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}
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static void
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tic6x_supply_register (struct regcache *regcache, int regno,
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const union tic6x_register *reg)
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{
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int offset = 0;
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supply_register (regcache, regno, reg->buf + offset);
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}
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static void
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tic6x_fill_gregset (struct regcache *regcache, void *buf)
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{
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auto regset = static_cast<union tic6x_register *> (buf);
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int i;
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for (i = 0; i < TIC6X_NUM_REGS; i++)
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if (tic6x_regmap[i] != -1)
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tic6x_collect_register (regcache, i, regset + tic6x_regmap[i]);
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}
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static void
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tic6x_store_gregset (struct regcache *regcache, const void *buf)
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{
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const auto regset = static_cast<const union tic6x_register *> (buf);
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int i;
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for (i = 0; i < TIC6X_NUM_REGS; i++)
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if (tic6x_regmap[i] != -1)
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tic6x_supply_register (regcache, i, regset + tic6x_regmap[i]);
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}
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static struct regset_info tic6x_regsets[] = {
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{ PTRACE_GETREGS, PTRACE_SETREGS, 0, TIC6X_NUM_REGS * 4, GENERAL_REGS,
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tic6x_fill_gregset, tic6x_store_gregset },
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NULL_REGSET
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};
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void
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tic6x_target::low_arch_setup ()
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{
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register unsigned int csr asm ("B2");
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unsigned int cpuid;
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enum c6x_feature feature = C6X_CORE;
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/* Determine the CPU we're running on to find the register order. */
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__asm__ ("MVC .S2 CSR,%0" : "=r" (csr) :);
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cpuid = csr >> 24;
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switch (cpuid)
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{
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case 0x00: /* C62x */
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case 0x02: /* C67x */
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tic6x_regmap = tic6x_regmap_c62x;
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tic6x_breakpoint = 0x0000a122; /* BNOP .S2 0,5 */
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feature = C6X_CORE;
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break;
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case 0x03: /* C67x+ */
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tic6x_regmap = tic6x_regmap_c64x;
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tic6x_breakpoint = 0x0000a122; /* BNOP .S2 0,5 */
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feature = C6X_GP;
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break;
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case 0x0c: /* C64x */
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tic6x_regmap = tic6x_regmap_c64x;
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tic6x_breakpoint = 0x0000a122; /* BNOP .S2 0,5 */
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feature = C6X_GP;
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break;
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case 0x10: /* C64x+ */
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case 0x14: /* C674x */
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case 0x15: /* C66x */
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tic6x_regmap = tic6x_regmap_c64xp;
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tic6x_breakpoint = 0x56454314; /* illegal opcode */
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feature = C6X_C6XP;
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break;
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default:
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error ("Unknown CPU ID 0x%02x", cpuid);
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}
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tic6x_usrregs_info.regmap = tic6x_regmap;
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current_process ()->tdesc = tic6x_read_description (feature);
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}
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static struct regsets_info tic6x_regsets_info =
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{
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tic6x_regsets, /* regsets */
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0, /* num_regsets */
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NULL, /* disabled_regsets */
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};
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static struct regs_info myregs_info =
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{
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NULL, /* regset_bitmap */
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&tic6x_usrregs_info,
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&tic6x_regsets_info
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};
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const regs_info *
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tic6x_target::get_regs_info ()
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{
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return &myregs_info;
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}
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#if GDB_SELF_TEST
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#include "gdbsupport/selftest.h"
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namespace selftests {
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namespace tdesc {
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static void
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tic6x_tdesc_test ()
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{
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SELF_CHECK (*tdesc_tic6x_c62x_linux == *tic6x_read_description (C6X_CORE));
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SELF_CHECK (*tdesc_tic6x_c64x_linux == *tic6x_read_description (C6X_GP));
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SELF_CHECK (*tdesc_tic6x_c64xp_linux == *tic6x_read_description (C6X_C6XP));
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}
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}
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}
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#endif
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/* The linux target ops object. */
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linux_process_target *the_linux_target = &the_tic6x_target;
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void
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initialize_low_arch (void)
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{
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#if GDB_SELF_TEST
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/* Initialize the Linux target descriptions. */
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init_registers_tic6x_c64xp_linux ();
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init_registers_tic6x_c64x_linux ();
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init_registers_tic6x_c62x_linux ();
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selftests::register_test ("tic6x-tdesc", selftests::tdesc::tic6x_tdesc_test);
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#endif
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initialize_regsets_info (&tic6x_regsets_info);
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}
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