mirror of
https://sourceware.org/git/binutils-gdb.git
synced 2024-12-27 04:52:05 +08:00
1368b914e9
Now that all port tests live under testsuite/sim/*/, and none live in testsuite/ directly, flatten the structure by moving all of the dirs under testsuite/sim/ to testsuite/ directly. We need to stop passing --tool to dejagnu so that it searches all dirs and not just ones that start with "sim". Since we have no other dirs in this tree, and no plans to add any, should be fine.
491 lines
9.1 KiB
Plaintext
491 lines
9.1 KiB
Plaintext
# frv testcase for cfckug $FCCi,$CCj_float,$CCi,$cond
|
|
# mach: all
|
|
|
|
.include "testutils.inc"
|
|
|
|
start
|
|
|
|
.global cfckug
|
|
cfckug:
|
|
set_spr_immed 0x1b5b,cccr
|
|
set_fcc 0x0 0
|
|
cfckug fcc0,cc3,cc0,1
|
|
test_spr_immed 0x1b9b,cccr
|
|
|
|
set_spr_immed 0x1b5b,cccr
|
|
set_fcc 0x1 0
|
|
cfckug fcc0,cc3,cc0,1
|
|
test_spr_immed 0x1bdb,cccr
|
|
|
|
set_spr_immed 0x1b5b,cccr
|
|
set_fcc 0x2 0
|
|
cfckug fcc0,cc3,cc0,1
|
|
test_spr_immed 0x1bdb,cccr
|
|
|
|
set_spr_immed 0x1b5b,cccr
|
|
set_fcc 0x3 0
|
|
cfckug fcc0,cc3,cc0,1
|
|
test_spr_immed 0x1bdb,cccr
|
|
|
|
set_spr_immed 0x1b5b,cccr
|
|
set_fcc 0x4 0
|
|
cfckug fcc0,cc3,cc0,1
|
|
test_spr_immed 0x1b9b,cccr
|
|
|
|
set_spr_immed 0x1b5b,cccr
|
|
set_fcc 0x5 0
|
|
cfckug fcc0,cc3,cc0,1
|
|
test_spr_immed 0x1bdb,cccr
|
|
|
|
set_spr_immed 0x1b5b,cccr
|
|
set_fcc 0x6 0
|
|
cfckug fcc0,cc3,cc0,1
|
|
test_spr_immed 0x1bdb,cccr
|
|
|
|
set_spr_immed 0x1b5b,cccr
|
|
set_fcc 0x7 0
|
|
cfckug fcc0,cc3,cc0,1
|
|
test_spr_immed 0x1bdb,cccr
|
|
|
|
set_spr_immed 0x1b5b,cccr
|
|
set_fcc 0x8 0
|
|
cfckug fcc0,cc3,cc4,1
|
|
test_spr_immed 0x1b9b,cccr
|
|
|
|
set_spr_immed 0x1b5b,cccr
|
|
set_fcc 0x9 0
|
|
cfckug fcc0,cc3,cc4,1
|
|
test_spr_immed 0x1bdb,cccr
|
|
|
|
set_spr_immed 0x1b5b,cccr
|
|
set_fcc 0xa 0
|
|
cfckug fcc0,cc3,cc4,1
|
|
test_spr_immed 0x1bdb,cccr
|
|
|
|
set_spr_immed 0x1b5b,cccr
|
|
set_fcc 0xb 0
|
|
cfckug fcc0,cc3,cc4,1
|
|
test_spr_immed 0x1bdb,cccr
|
|
|
|
set_spr_immed 0x1b5b,cccr
|
|
set_fcc 0xc 0
|
|
cfckug fcc0,cc3,cc4,1
|
|
test_spr_immed 0x1b9b,cccr
|
|
|
|
set_spr_immed 0x1b5b,cccr
|
|
set_fcc 0xd 0
|
|
cfckug fcc0,cc3,cc4,1
|
|
test_spr_immed 0x1bdb,cccr
|
|
|
|
set_spr_immed 0x1b5b,cccr
|
|
set_fcc 0xe 0
|
|
cfckug fcc0,cc3,cc4,1
|
|
test_spr_immed 0x1bdb,cccr
|
|
|
|
set_spr_immed 0x1b5b,cccr
|
|
set_fcc 0xf 0
|
|
cfckug fcc0,cc3,cc4,1
|
|
test_spr_immed 0x1bdb,cccr
|
|
|
|
set_spr_immed 0x1b5b,cccr
|
|
set_fcc 0x0 0
|
|
cfckug fcc0,cc3,cc0,0
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x1b5b,cccr
|
|
set_fcc 0x1 0
|
|
cfckug fcc0,cc3,cc0,0
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x1b5b,cccr
|
|
set_fcc 0x2 0
|
|
cfckug fcc0,cc3,cc0,0
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x1b5b,cccr
|
|
set_fcc 0x3 0
|
|
cfckug fcc0,cc3,cc0,0
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x1b5b,cccr
|
|
set_fcc 0x4 0
|
|
cfckug fcc0,cc3,cc0,0
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x1b5b,cccr
|
|
set_fcc 0x5 0
|
|
cfckug fcc0,cc3,cc0,0
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x1b5b,cccr
|
|
set_fcc 0x6 0
|
|
cfckug fcc0,cc3,cc0,0
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x1b5b,cccr
|
|
set_fcc 0x7 0
|
|
cfckug fcc0,cc3,cc0,0
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x1b5b,cccr
|
|
set_fcc 0x8 0
|
|
cfckug fcc0,cc3,cc4,0
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x1b5b,cccr
|
|
set_fcc 0x9 0
|
|
cfckug fcc0,cc3,cc4,0
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x1b5b,cccr
|
|
set_fcc 0xa 0
|
|
cfckug fcc0,cc3,cc4,0
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x1b5b,cccr
|
|
set_fcc 0xb 0
|
|
cfckug fcc0,cc3,cc4,0
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x1b5b,cccr
|
|
set_fcc 0xc 0
|
|
cfckug fcc0,cc3,cc4,0
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x1b5b,cccr
|
|
set_fcc 0xd 0
|
|
cfckug fcc0,cc3,cc4,0
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x1b5b,cccr
|
|
set_fcc 0xe 0
|
|
cfckug fcc0,cc3,cc4,0
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x1b5b,cccr
|
|
set_fcc 0xf 0
|
|
cfckug fcc0,cc3,cc4,0
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x1b5b,cccr
|
|
set_fcc 0x0 0
|
|
cfckug fcc0,cc3,cc1,0
|
|
test_spr_immed 0x1b9b,cccr
|
|
|
|
set_spr_immed 0x1b5b,cccr
|
|
set_fcc 0x1 0
|
|
cfckug fcc0,cc3,cc1,0
|
|
test_spr_immed 0x1bdb,cccr
|
|
|
|
set_spr_immed 0x1b5b,cccr
|
|
set_fcc 0x2 0
|
|
cfckug fcc0,cc3,cc1,0
|
|
test_spr_immed 0x1bdb,cccr
|
|
|
|
set_spr_immed 0x1b5b,cccr
|
|
set_fcc 0x3 0
|
|
cfckug fcc0,cc3,cc1,0
|
|
test_spr_immed 0x1bdb,cccr
|
|
|
|
set_spr_immed 0x1b5b,cccr
|
|
set_fcc 0x4 0
|
|
cfckug fcc0,cc3,cc1,0
|
|
test_spr_immed 0x1b9b,cccr
|
|
|
|
set_spr_immed 0x1b5b,cccr
|
|
set_fcc 0x5 0
|
|
cfckug fcc0,cc3,cc1,0
|
|
test_spr_immed 0x1bdb,cccr
|
|
|
|
set_spr_immed 0x1b5b,cccr
|
|
set_fcc 0x6 0
|
|
cfckug fcc0,cc3,cc1,0
|
|
test_spr_immed 0x1bdb,cccr
|
|
|
|
set_spr_immed 0x1b5b,cccr
|
|
set_fcc 0x7 0
|
|
cfckug fcc0,cc3,cc1,0
|
|
test_spr_immed 0x1bdb,cccr
|
|
|
|
set_spr_immed 0x1b5b,cccr
|
|
set_fcc 0x8 0
|
|
cfckug fcc0,cc3,cc5,0
|
|
test_spr_immed 0x1b9b,cccr
|
|
|
|
set_spr_immed 0x1b5b,cccr
|
|
set_fcc 0x9 0
|
|
cfckug fcc0,cc3,cc5,0
|
|
test_spr_immed 0x1bdb,cccr
|
|
|
|
set_spr_immed 0x1b5b,cccr
|
|
set_fcc 0xa 0
|
|
cfckug fcc0,cc3,cc5,0
|
|
test_spr_immed 0x1bdb,cccr
|
|
|
|
set_spr_immed 0x1b5b,cccr
|
|
set_fcc 0xb 0
|
|
cfckug fcc0,cc3,cc5,0
|
|
test_spr_immed 0x1bdb,cccr
|
|
|
|
set_spr_immed 0x1b5b,cccr
|
|
set_fcc 0xc 0
|
|
cfckug fcc0,cc3,cc5,0
|
|
test_spr_immed 0x1b9b,cccr
|
|
|
|
set_spr_immed 0x1b5b,cccr
|
|
set_fcc 0xd 0
|
|
cfckug fcc0,cc3,cc5,0
|
|
test_spr_immed 0x1bdb,cccr
|
|
|
|
set_spr_immed 0x1b5b,cccr
|
|
set_fcc 0xe 0
|
|
cfckug fcc0,cc3,cc5,0
|
|
test_spr_immed 0x1bdb,cccr
|
|
|
|
set_spr_immed 0x1b5b,cccr
|
|
set_fcc 0xf 0
|
|
cfckug fcc0,cc3,cc5,0
|
|
test_spr_immed 0x1bdb,cccr
|
|
|
|
set_spr_immed 0x1b5b,cccr
|
|
set_fcc 0x0 0
|
|
cfckug fcc0,cc3,cc1,1
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x1b5b,cccr
|
|
set_fcc 0x1 0
|
|
cfckug fcc0,cc3,cc1,1
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x1b5b,cccr
|
|
set_fcc 0x2 0
|
|
cfckug fcc0,cc3,cc1,1
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x1b5b,cccr
|
|
set_fcc 0x3 0
|
|
cfckug fcc0,cc3,cc1,1
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x1b5b,cccr
|
|
set_fcc 0x4 0
|
|
cfckug fcc0,cc3,cc1,1
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x1b5b,cccr
|
|
set_fcc 0x5 0
|
|
cfckug fcc0,cc3,cc1,1
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x1b5b,cccr
|
|
set_fcc 0x6 0
|
|
cfckug fcc0,cc3,cc1,1
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x1b5b,cccr
|
|
set_fcc 0x7 0
|
|
cfckug fcc0,cc3,cc1,1
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x1b5b,cccr
|
|
set_fcc 0x8 0
|
|
cfckug fcc0,cc3,cc5,1
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x1b5b,cccr
|
|
set_fcc 0x9 0
|
|
cfckug fcc0,cc3,cc5,1
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x1b5b,cccr
|
|
set_fcc 0xa 0
|
|
cfckug fcc0,cc3,cc5,1
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x1b5b,cccr
|
|
set_fcc 0xb 0
|
|
cfckug fcc0,cc3,cc5,1
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x1b5b,cccr
|
|
set_fcc 0xc 0
|
|
cfckug fcc0,cc3,cc5,1
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x1b5b,cccr
|
|
set_fcc 0xd 0
|
|
cfckug fcc0,cc3,cc5,1
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x1b5b,cccr
|
|
set_fcc 0xe 0
|
|
cfckug fcc0,cc3,cc5,1
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x1b5b,cccr
|
|
set_fcc 0xf 0
|
|
cfckug fcc0,cc3,cc5,1
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x1b5b,cccr
|
|
set_fcc 0x0 0
|
|
cfckug fcc0,cc3,cc2,0
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x1b5b,cccr
|
|
set_fcc 0x1 0
|
|
cfckug fcc0,cc3,cc2,1
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x1b5b,cccr
|
|
set_fcc 0x2 0
|
|
cfckug fcc0,cc3,cc2,0
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x1b5b,cccr
|
|
set_fcc 0x3 0
|
|
cfckug fcc0,cc3,cc2,1
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x1b5b,cccr
|
|
set_fcc 0x4 0
|
|
cfckug fcc0,cc3,cc2,0
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x1b5b,cccr
|
|
set_fcc 0x5 0
|
|
cfckug fcc0,cc3,cc2,1
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x1b5b,cccr
|
|
set_fcc 0x6 0
|
|
cfckug fcc0,cc3,cc2,0
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x1b5b,cccr
|
|
set_fcc 0x7 0
|
|
cfckug fcc0,cc3,cc2,1
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x1b5b,cccr
|
|
set_fcc 0x8 0
|
|
cfckug fcc0,cc3,cc6,0
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x1b5b,cccr
|
|
set_fcc 0x9 0
|
|
cfckug fcc0,cc3,cc6,1
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x1b5b,cccr
|
|
set_fcc 0xa 0
|
|
cfckug fcc0,cc3,cc6,0
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x1b5b,cccr
|
|
set_fcc 0xb 0
|
|
cfckug fcc0,cc3,cc6,1
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x1b5b,cccr
|
|
set_fcc 0xc 0
|
|
cfckug fcc0,cc3,cc6,0
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x1b5b,cccr
|
|
set_fcc 0xd 0
|
|
cfckug fcc0,cc3,cc6,1
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x1b5b,cccr
|
|
set_fcc 0xe 0
|
|
cfckug fcc0,cc3,cc6,0
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x1b5b,cccr
|
|
set_fcc 0xf 0
|
|
cfckug fcc0,cc3,cc6,1
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x1b5b,cccr
|
|
set_fcc 0x0 0
|
|
cfckug fcc0,cc3,cc3,0
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x1b5b,cccr
|
|
set_fcc 0x1 0
|
|
cfckug fcc0,cc3,cc3,1
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x1b5b,cccr
|
|
set_fcc 0x2 0
|
|
cfckug fcc0,cc3,cc3,0
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x1b5b,cccr
|
|
set_fcc 0x3 0
|
|
cfckug fcc0,cc3,cc3,1
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x1b5b,cccr
|
|
set_fcc 0x4 0
|
|
cfckug fcc0,cc3,cc3,0
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x1b5b,cccr
|
|
set_fcc 0x5 0
|
|
cfckug fcc0,cc3,cc3,1
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x1b5b,cccr
|
|
set_fcc 0x6 0
|
|
cfckug fcc0,cc3,cc3,0
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x1b5b,cccr
|
|
set_fcc 0x7 0
|
|
cfckug fcc0,cc3,cc3,1
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x1b5b,cccr
|
|
set_fcc 0x8 0
|
|
cfckug fcc0,cc3,cc7,0
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x1b5b,cccr
|
|
set_fcc 0x9 0
|
|
cfckug fcc0,cc3,cc7,1
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x1b5b,cccr
|
|
set_fcc 0xa 0
|
|
cfckug fcc0,cc3,cc7,0
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x1b5b,cccr
|
|
set_fcc 0xb 0
|
|
cfckug fcc0,cc3,cc7,1
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x1b5b,cccr
|
|
set_fcc 0xc 0
|
|
cfckug fcc0,cc3,cc7,0
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x1b5b,cccr
|
|
set_fcc 0xd 0
|
|
cfckug fcc0,cc3,cc7,1
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x1b5b,cccr
|
|
set_fcc 0xe 0
|
|
cfckug fcc0,cc3,cc7,0
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x1b5b,cccr
|
|
set_fcc 0xf 0
|
|
cfckug fcc0,cc3,cc7,1
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
pass
|