mirror of
https://sourceware.org/git/binutils-gdb.git
synced 2024-12-27 04:52:05 +08:00
1368b914e9
Now that all port tests live under testsuite/sim/*/, and none live in testsuite/ directly, flatten the structure by moving all of the dirs under testsuite/sim/ to testsuite/ directly. We need to stop passing --tool to dejagnu so that it searches all dirs and not just ones that start with "sim". Since we have no other dirs in this tree, and no plans to add any, should be fine.
491 lines
8.9 KiB
Plaintext
491 lines
8.9 KiB
Plaintext
# frv testcase for cckp $ICCi,$CCj_int,$CCi,$cond
|
|
# mach: all
|
|
|
|
.include "testutils.inc"
|
|
|
|
start
|
|
|
|
.global cckp
|
|
cckp:
|
|
set_spr_immed 0x5b1b,cccr
|
|
set_icc 0x0 0
|
|
cckp icc0,cc7,cc0,1
|
|
test_spr_immed 0xdb1b,cccr
|
|
|
|
set_spr_immed 0x5b1b,cccr
|
|
set_icc 0x1 0
|
|
cckp icc0,cc7,cc0,1
|
|
test_spr_immed 0xdb1b,cccr
|
|
|
|
set_spr_immed 0x5b1b,cccr
|
|
set_icc 0x2 0
|
|
cckp icc0,cc7,cc0,1
|
|
test_spr_immed 0xdb1b,cccr
|
|
|
|
set_spr_immed 0x5b1b,cccr
|
|
set_icc 0x3 0
|
|
cckp icc0,cc7,cc0,1
|
|
test_spr_immed 0xdb1b,cccr
|
|
|
|
set_spr_immed 0x5b1b,cccr
|
|
set_icc 0x4 0
|
|
cckp icc0,cc7,cc0,1
|
|
test_spr_immed 0xdb1b,cccr
|
|
|
|
set_spr_immed 0x5b1b,cccr
|
|
set_icc 0x5 0
|
|
cckp icc0,cc7,cc0,1
|
|
test_spr_immed 0xdb1b,cccr
|
|
|
|
set_spr_immed 0x5b1b,cccr
|
|
set_icc 0x6 0
|
|
cckp icc0,cc7,cc0,1
|
|
test_spr_immed 0xdb1b,cccr
|
|
|
|
set_spr_immed 0x5b1b,cccr
|
|
set_icc 0x7 0
|
|
cckp icc0,cc7,cc0,1
|
|
test_spr_immed 0xdb1b,cccr
|
|
|
|
set_spr_immed 0x5b1b,cccr
|
|
set_icc 0x8 0
|
|
cckp icc0,cc7,cc4,1
|
|
test_spr_immed 0x9b1b,cccr
|
|
|
|
set_spr_immed 0x5b1b,cccr
|
|
set_icc 0x9 0
|
|
cckp icc0,cc7,cc4,1
|
|
test_spr_immed 0x9b1b,cccr
|
|
|
|
set_spr_immed 0x5b1b,cccr
|
|
set_icc 0xa 0
|
|
cckp icc0,cc7,cc4,1
|
|
test_spr_immed 0x9b1b,cccr
|
|
|
|
set_spr_immed 0x5b1b,cccr
|
|
set_icc 0xb 0
|
|
cckp icc0,cc7,cc4,1
|
|
test_spr_immed 0x9b1b,cccr
|
|
|
|
set_spr_immed 0x5b1b,cccr
|
|
set_icc 0xc 0
|
|
cckp icc0,cc7,cc4,1
|
|
test_spr_immed 0x9b1b,cccr
|
|
|
|
set_spr_immed 0x5b1b,cccr
|
|
set_icc 0xd 0
|
|
cckp icc0,cc7,cc4,1
|
|
test_spr_immed 0x9b1b,cccr
|
|
|
|
set_spr_immed 0x5b1b,cccr
|
|
set_icc 0xe 0
|
|
cckp icc0,cc7,cc4,1
|
|
test_spr_immed 0x9b1b,cccr
|
|
|
|
set_spr_immed 0x5b1b,cccr
|
|
set_icc 0xf 0
|
|
cckp icc0,cc7,cc4,1
|
|
test_spr_immed 0x9b1b,cccr
|
|
|
|
set_spr_immed 0x5b1b,cccr
|
|
set_icc 0x0 0
|
|
cckp icc0,cc7,cc0,0
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x5b1b,cccr
|
|
set_icc 0x1 0
|
|
cckp icc0,cc7,cc0,0
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x5b1b,cccr
|
|
set_icc 0x2 0
|
|
cckp icc0,cc7,cc0,0
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x5b1b,cccr
|
|
set_icc 0x3 0
|
|
cckp icc0,cc7,cc0,0
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x5b1b,cccr
|
|
set_icc 0x4 0
|
|
cckp icc0,cc7,cc0,0
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x5b1b,cccr
|
|
set_icc 0x5 0
|
|
cckp icc0,cc7,cc0,0
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x5b1b,cccr
|
|
set_icc 0x6 0
|
|
cckp icc0,cc7,cc0,0
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x5b1b,cccr
|
|
set_icc 0x7 0
|
|
cckp icc0,cc7,cc0,0
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x5b1b,cccr
|
|
set_icc 0x8 0
|
|
cckp icc0,cc7,cc4,0
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x5b1b,cccr
|
|
set_icc 0x9 0
|
|
cckp icc0,cc7,cc4,0
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x5b1b,cccr
|
|
set_icc 0xa 0
|
|
cckp icc0,cc7,cc4,0
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x5b1b,cccr
|
|
set_icc 0xb 0
|
|
cckp icc0,cc7,cc4,0
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x5b1b,cccr
|
|
set_icc 0xc 0
|
|
cckp icc0,cc7,cc4,0
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x5b1b,cccr
|
|
set_icc 0xd 0
|
|
cckp icc0,cc7,cc4,0
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x5b1b,cccr
|
|
set_icc 0xe 0
|
|
cckp icc0,cc7,cc4,0
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x5b1b,cccr
|
|
set_icc 0xf 0
|
|
cckp icc0,cc7,cc4,0
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x5b1b,cccr
|
|
set_icc 0x0 0
|
|
cckp icc0,cc7,cc1,0
|
|
test_spr_immed 0xdb1b,cccr
|
|
|
|
set_spr_immed 0x5b1b,cccr
|
|
set_icc 0x1 0
|
|
cckp icc0,cc7,cc1,0
|
|
test_spr_immed 0xdb1b,cccr
|
|
|
|
set_spr_immed 0x5b1b,cccr
|
|
set_icc 0x2 0
|
|
cckp icc0,cc7,cc1,0
|
|
test_spr_immed 0xdb1b,cccr
|
|
|
|
set_spr_immed 0x5b1b,cccr
|
|
set_icc 0x3 0
|
|
cckp icc0,cc7,cc1,0
|
|
test_spr_immed 0xdb1b,cccr
|
|
|
|
set_spr_immed 0x5b1b,cccr
|
|
set_icc 0x4 0
|
|
cckp icc0,cc7,cc1,0
|
|
test_spr_immed 0xdb1b,cccr
|
|
|
|
set_spr_immed 0x5b1b,cccr
|
|
set_icc 0x5 0
|
|
cckp icc0,cc7,cc1,0
|
|
test_spr_immed 0xdb1b,cccr
|
|
|
|
set_spr_immed 0x5b1b,cccr
|
|
set_icc 0x6 0
|
|
cckp icc0,cc7,cc1,0
|
|
test_spr_immed 0xdb1b,cccr
|
|
|
|
set_spr_immed 0x5b1b,cccr
|
|
set_icc 0x7 0
|
|
cckp icc0,cc7,cc1,0
|
|
test_spr_immed 0xdb1b,cccr
|
|
|
|
set_spr_immed 0x5b1b,cccr
|
|
set_icc 0x8 0
|
|
cckp icc0,cc7,cc5,0
|
|
test_spr_immed 0x9b1b,cccr
|
|
|
|
set_spr_immed 0x5b1b,cccr
|
|
set_icc 0x9 0
|
|
cckp icc0,cc7,cc5,0
|
|
test_spr_immed 0x9b1b,cccr
|
|
|
|
set_spr_immed 0x5b1b,cccr
|
|
set_icc 0xa 0
|
|
cckp icc0,cc7,cc5,0
|
|
test_spr_immed 0x9b1b,cccr
|
|
|
|
set_spr_immed 0x5b1b,cccr
|
|
set_icc 0xb 0
|
|
cckp icc0,cc7,cc5,0
|
|
test_spr_immed 0x9b1b,cccr
|
|
|
|
set_spr_immed 0x5b1b,cccr
|
|
set_icc 0xc 0
|
|
cckp icc0,cc7,cc5,0
|
|
test_spr_immed 0x9b1b,cccr
|
|
|
|
set_spr_immed 0x5b1b,cccr
|
|
set_icc 0xd 0
|
|
cckp icc0,cc7,cc5,0
|
|
test_spr_immed 0x9b1b,cccr
|
|
|
|
set_spr_immed 0x5b1b,cccr
|
|
set_icc 0xe 0
|
|
cckp icc0,cc7,cc5,0
|
|
test_spr_immed 0x9b1b,cccr
|
|
|
|
set_spr_immed 0x5b1b,cccr
|
|
set_icc 0xf 0
|
|
cckp icc0,cc7,cc5,0
|
|
test_spr_immed 0x9b1b,cccr
|
|
|
|
set_spr_immed 0x5b1b,cccr
|
|
set_icc 0x0 0
|
|
cckp icc0,cc7,cc1,1
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x5b1b,cccr
|
|
set_icc 0x1 0
|
|
cckp icc0,cc7,cc1,1
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x5b1b,cccr
|
|
set_icc 0x2 0
|
|
cckp icc0,cc7,cc1,1
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x5b1b,cccr
|
|
set_icc 0x3 0
|
|
cckp icc0,cc7,cc1,1
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x5b1b,cccr
|
|
set_icc 0x4 0
|
|
cckp icc0,cc7,cc1,1
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x5b1b,cccr
|
|
set_icc 0x5 0
|
|
cckp icc0,cc7,cc1,1
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x5b1b,cccr
|
|
set_icc 0x6 0
|
|
cckp icc0,cc7,cc1,1
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x5b1b,cccr
|
|
set_icc 0x7 0
|
|
cckp icc0,cc7,cc1,1
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x5b1b,cccr
|
|
set_icc 0x8 0
|
|
cckp icc0,cc7,cc5,1
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x5b1b,cccr
|
|
set_icc 0x9 0
|
|
cckp icc0,cc7,cc5,1
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x5b1b,cccr
|
|
set_icc 0xa 0
|
|
cckp icc0,cc7,cc5,1
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x5b1b,cccr
|
|
set_icc 0xb 0
|
|
cckp icc0,cc7,cc5,1
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x5b1b,cccr
|
|
set_icc 0xc 0
|
|
cckp icc0,cc7,cc5,1
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x5b1b,cccr
|
|
set_icc 0xd 0
|
|
cckp icc0,cc7,cc5,1
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x5b1b,cccr
|
|
set_icc 0xe 0
|
|
cckp icc0,cc7,cc5,1
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x5b1b,cccr
|
|
set_icc 0xf 0
|
|
cckp icc0,cc7,cc5,1
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x5b1b,cccr
|
|
set_icc 0x0 0
|
|
cckp icc0,cc7,cc2,0
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x5b1b,cccr
|
|
set_icc 0x1 0
|
|
cckp icc0,cc7,cc2,1
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x5b1b,cccr
|
|
set_icc 0x2 0
|
|
cckp icc0,cc7,cc2,0
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x5b1b,cccr
|
|
set_icc 0x3 0
|
|
cckp icc0,cc7,cc2,1
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x5b1b,cccr
|
|
set_icc 0x4 0
|
|
cckp icc0,cc7,cc2,0
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x5b1b,cccr
|
|
set_icc 0x5 0
|
|
cckp icc0,cc7,cc2,1
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x5b1b,cccr
|
|
set_icc 0x6 0
|
|
cckp icc0,cc7,cc2,0
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x5b1b,cccr
|
|
set_icc 0x7 0
|
|
cckp icc0,cc7,cc2,1
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x5b1b,cccr
|
|
set_icc 0x8 0
|
|
cckp icc0,cc7,cc6,0
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x5b1b,cccr
|
|
set_icc 0x9 0
|
|
cckp icc0,cc7,cc6,1
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x5b1b,cccr
|
|
set_icc 0xa 0
|
|
cckp icc0,cc7,cc6,0
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x5b1b,cccr
|
|
set_icc 0xb 0
|
|
cckp icc0,cc7,cc6,1
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x5b1b,cccr
|
|
set_icc 0xc 0
|
|
cckp icc0,cc7,cc6,0
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x5b1b,cccr
|
|
set_icc 0xd 0
|
|
cckp icc0,cc7,cc6,1
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x5b1b,cccr
|
|
set_icc 0xe 0
|
|
cckp icc0,cc7,cc6,0
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x5b1b,cccr
|
|
set_icc 0xf 0
|
|
cckp icc0,cc7,cc6,1
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x5b1b,cccr
|
|
set_icc 0x0 0
|
|
cckp icc0,cc7,cc3,0
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x5b1b,cccr
|
|
set_icc 0x1 0
|
|
cckp icc0,cc7,cc3,1
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x5b1b,cccr
|
|
set_icc 0x2 0
|
|
cckp icc0,cc7,cc3,0
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x5b1b,cccr
|
|
set_icc 0x3 0
|
|
cckp icc0,cc7,cc3,1
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x5b1b,cccr
|
|
set_icc 0x4 0
|
|
cckp icc0,cc7,cc3,0
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x5b1b,cccr
|
|
set_icc 0x5 0
|
|
cckp icc0,cc7,cc3,1
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x5b1b,cccr
|
|
set_icc 0x6 0
|
|
cckp icc0,cc7,cc3,0
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x5b1b,cccr
|
|
set_icc 0x7 0
|
|
cckp icc0,cc7,cc3,1
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x5b1b,cccr
|
|
set_icc 0x8 0
|
|
cckp icc0,cc7,cc7,0
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x5b1b,cccr
|
|
set_icc 0x9 0
|
|
cckp icc0,cc7,cc7,1
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x5b1b,cccr
|
|
set_icc 0xa 0
|
|
cckp icc0,cc7,cc7,0
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x5b1b,cccr
|
|
set_icc 0xb 0
|
|
cckp icc0,cc7,cc7,1
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x5b1b,cccr
|
|
set_icc 0xc 0
|
|
cckp icc0,cc7,cc7,0
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x5b1b,cccr
|
|
set_icc 0xd 0
|
|
cckp icc0,cc7,cc7,1
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x5b1b,cccr
|
|
set_icc 0xe 0
|
|
cckp icc0,cc7,cc7,0
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
set_spr_immed 0x5b1b,cccr
|
|
set_icc 0xf 0
|
|
cckp icc0,cc7,cc7,1
|
|
test_spr_immed 0x1b1b,cccr
|
|
|
|
pass
|