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b8a9943dd4
(extract.o): Pass -DSCACHE_P.
* mloop.in (extract{16,32}): Update call to m32r_decode.
* arch.h,cpu.h,cpuall.h,decode.[ch]: Regenerate.
* extract.c,model.c,sem-switch.c,sem.c: Regenerate.
* sim-main.h: #include "ansidecl.h".
Don't include cpu-opc.h, done by arch.h.
start-sanitize-m32rx
* Makefile.in (M32RX_OBJS): Build m32rx support now.
(m32rx.o): New rule.
* m32r-sim.h (m32rx_h_cr_[gs]et): Define.
* m32rx.c (m32rx_{fetch,store}_register): Update {get,set} of PC.
(m32rx_h_accums_get): New function.
* mloopx.in: Update call to m32rx_decode. Rewrite exec loop.
* cpux.h,decodex.[ch],modelx.c,readx.c,semx.c: Regenerate.
end-sanitize-m32rx
156 lines
5.1 KiB
Makefile
156 lines
5.1 KiB
Makefile
# Makefile template for Configure for the m32r simulator
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# Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
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# Contributed by Cygnus Support.
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#
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# This file is part of GDB, the GNU debugger.
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; either version 2 of the License, or
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# (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License along
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# with this program; if not, write to the Free Software Foundation, Inc.,
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# 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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## COMMON_PRE_CONFIG_FRAG
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M32R_OBJS = m32r.o decode.o extract.o sem.o model.o mloop.o
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# start-sanitize-m32rx
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M32RX_OBJS = m32rx.o decodex.o semx.o modelx.o mloopx.o
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# end-sanitize-m32rx
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SIM_OBJS = \
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$(SIM_NEW_COMMON_OBJS) \
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sim-hload.o sim-hrw.o sim-engine.o sim-model.o sim-reason.o \
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cgen-utils.o cgen-trace.o cgen-scache.o \
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sim-if.o arch.o \
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$(start-sanitize-m32rx) \
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$(M32RX_OBJS) \
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$(end-sanitize-m32rx) \
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$(M32R_OBJS)
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# Extra headers included by sim-main.h.
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SIM_EXTRA_DEPS = \
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$(srcdir)/../common/cgen-types.h \
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$(srcdir)/../common/cgen-sim.h \
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$(srcdir)/../common/cgen-trace.h \
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arch.h cpuall.h m32r-sim.h
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SIM_EXTRA_CFLAGS =
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SIM_RUN_OBJS = nrun.o
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SIM_EXTRA_CLEAN = m32r-clean
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## COMMON_POST_CONFIG_FRAG
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arch = m32r
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MAIN_INCLUDE_DEPS = \
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sim-main.h \
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$(srcdir)/../common/sim-config.h \
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$(srcdir)/../common/sim-base.h \
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$(srcdir)/../common/sim-basics.h \
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$(srcdir)/../common/sim-module.h \
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$(srcdir)/../common/sim-trace.h \
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$(srcdir)/../common/sim-profile.h \
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tconfig.h
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INCLUDE_DEPS = $(MAIN_INCLUDE_DEPS) $(SIM_EXTRA_DEPS) cpu-sim.h
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OPS_INCLUDE_DEPS = \
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$(srcdir)/../common/cgen-mem.h \
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$(srcdir)/../common/cgen-ops.h
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sim-if.o: sim-if.c $(INCLUDE_DEPS) $(srcdir)/../common/sim-core.h
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arch.o: arch.c $(INCLUDE_DEPS) cpu-opc.h
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# M32R objs
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m32r.o: m32r.c $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpu.h
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# FIXME: Use of `mono' is wip.
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mloop.c: $(srcdir)/../common/genmloop.sh mloop.in Makefile
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rm -f mloop.c
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$(SHELL) $(srcdir)/../common/genmloop.sh $(SHELL) \
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-mono -scache -fast m32r $(srcdir)/mloop.in \
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| sed -e 's/@cpu@/m32r/' -e 's/@CPU@/M32R/' >mloop.c
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mloop.o: mloop.c sem-switch.c $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpu.h
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decode.o: decode.c decode.h $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpu-opc.h cpu.h
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extract.o: extract.c decode.h $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpu.h
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$(CC) -c $(srcdir)/extract.c $(ALL_CFLAGS) -DSCACHE_P
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sem.o: sem.c decode.h $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpu.h
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model.o: model.c $(INCLUDE_DEPS) cpu-opc.h cpu.h
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#sem-cache.o: sem.c decode.h $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpu.h
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# $(CC) -c $(srcdir)/sem.c -o sem-cache.o -DSCACHE_P $(ALL_CFLAGS)
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# start-sanitize-m32rx
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# M32RX objs
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m32rx.o: m32rx.c $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpux.h
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# FIXME: Use of `mono' is wip.
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mloopx.c: $(srcdir)/../common/genmloop.sh mloopx.in Makefile
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rm -f mloopx.c
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$(SHELL) $(srcdir)/../common/genmloop.sh $(SHELL) \
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-mono -no-scache -no-fast -no-parallel \
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m32r $(srcdir)/mloopx.in \
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| sed -e 's/@cpu@/m32rx/' -e 's/@CPU@/M32RX/' >mloopx.c
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mloopx.o: mloopx.c readx.c $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpux.h
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decodex.o: decodex.c decodex.h $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpu-opc.h cpux.h
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semx.o: semx.c decodex.h $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpux.h
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modelx.o: modelx.c $(INCLUDE_DEPS) cpu-opc.h cpux.h
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# end-sanitize-m32rx
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m32r-clean:
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rm -f mloop.c stamp-arch stamp-cpu stamp-decode
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# start-sanitize-m32rx
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rm -f mloopx.c stamp-xcpu stamp-xdecode
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# end-sanitize-m32rx
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rm -f tmp-*
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# start-sanitize-cygnus
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# cgen support
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# For now, require developers to configure with --enable-maintainer-mode.
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# ??? Do we need to use a different option?
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stamp-arch: $(CGEN_MAIN_SCM) $(srccgen)/m32r.cpu
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$(MAKE) cgen-arch
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touch stamp-arch
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arch.h arch.c cpuall.h: @MAINT@ stamp-arch
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@true
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stamp-cpu: $(CGEN_MAIN_SCM) $(CGEN_CPU_SCM) $(srccgen)/m32r.cpu
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$(MAKE) cgen-cpu cpu=m32r mach=m32r SUFFIX= FLAGS="with-scache,with-profile fn" EXTRAFILES="$(CGEN_CPU_EXTR) $(CGEN_CPU_SEM) $(CGEN_CPU_SEMSW)"
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touch stamp-cpu
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cpu.h extract.c sem.c sem-switch.c model.c: @MAINT@ stamp-cpu
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@true
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stamp-decode: $(CGEN_MAIN_SCM) $(CGEN_DECODE_SCM) $(srccgen)/m32r.cpu
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$(MAKE) cgen-decode cpu=m32r mach=m32r SUFFIX= FLAGS="with-scache,with-profile fn"
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touch stamp-decode
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decode.h decode.c: @MAINT@ stamp-decode
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@true
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# start-sanitize-cygnus
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# start-sanitize-m32rx
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stamp-xcpu: $(CGEN_MAIN_SCM) $(CGEN_CPU_SCM) $(srccgen)/m32r.cpu
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$(MAKE) cgen-cpu cpu=m32rx mach=m32rx SUFFIX=x FLAGS="" EXTRAFILES="$(CGEN_CPU_READ) $(CGEN_CPU_SEM)"
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touch stamp-xcpu
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cpux.h readx.c semx.c modelx.c: @MAINT@ stamp-xcpu
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@true
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stamp-xdecode: $(CGEN_MAIN_SCM) $(CGEN_DECODE_SCM) $(srccgen)/m32r.cpu
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$(MAKE) cgen-decode cpu=m32rx mach=m32rx SUFFIX=x
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touch stamp-xdecode
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decodex.h decodex.c: @MAINT@ stamp-xdecode
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@true
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# end-sanitize-m32rx
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