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393 lines
12 KiB
C
393 lines
12 KiB
C
/* Common target dependent for AArch64 systems.
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Copyright (C) 2018-2021 Free Software Foundation, Inc.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#include <sys/utsname.h>
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#include <sys/uio.h>
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#include "gdbsupport/common-defs.h"
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#include "elf/external.h"
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#include "elf/common.h"
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#include "aarch64-sve-linux-ptrace.h"
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#include "arch/aarch64.h"
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#include "gdbsupport/common-regcache.h"
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#include "gdbsupport/byte-vector.h"
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#include <endian.h>
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/* See nat/aarch64-sve-linux-ptrace.h. */
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uint64_t
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aarch64_sve_get_vq (int tid)
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{
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struct iovec iovec;
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struct user_sve_header header;
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iovec.iov_len = sizeof (header);
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iovec.iov_base = &header;
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/* Ptrace gives the vector length in bytes. Convert it to VQ, the number of
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128bit chunks in a Z register. We use VQ because 128bits is the minimum
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a Z register can increase in size. */
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if (ptrace (PTRACE_GETREGSET, tid, NT_ARM_SVE, &iovec) < 0)
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{
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/* SVE is not supported. */
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return 0;
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}
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uint64_t vq = sve_vq_from_vl (header.vl);
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if (!sve_vl_valid (header.vl))
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{
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warning (_("Invalid SVE state from kernel; SVE disabled."));
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return 0;
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}
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return vq;
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}
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/* See nat/aarch64-sve-linux-ptrace.h. */
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bool
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aarch64_sve_set_vq (int tid, uint64_t vq)
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{
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struct iovec iovec;
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struct user_sve_header header;
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iovec.iov_len = sizeof (header);
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iovec.iov_base = &header;
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if (ptrace (PTRACE_GETREGSET, tid, NT_ARM_SVE, &iovec) < 0)
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{
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/* SVE is not supported. */
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return false;
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}
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header.vl = sve_vl_from_vq (vq);
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if (ptrace (PTRACE_SETREGSET, tid, NT_ARM_SVE, &iovec) < 0)
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{
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/* Vector length change failed. */
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return false;
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}
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return true;
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}
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/* See nat/aarch64-sve-linux-ptrace.h. */
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bool
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aarch64_sve_set_vq (int tid, struct reg_buffer_common *reg_buf)
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{
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uint64_t reg_vg = 0;
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/* The VG register may not be valid if we've not collected any value yet.
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This can happen, for example, if we're restoring the regcache after an
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inferior function call, and the VG register comes after the Z
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registers. */
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if (reg_buf->get_register_status (AARCH64_SVE_VG_REGNUM) != REG_VALID)
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{
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/* If vg is not available yet, fetch it from ptrace. The VG value from
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ptrace is likely the correct one. */
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uint64_t vq = aarch64_sve_get_vq (tid);
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/* If something went wrong, just bail out. */
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if (vq == 0)
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return false;
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reg_vg = sve_vg_from_vq (vq);
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}
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else
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reg_buf->raw_collect (AARCH64_SVE_VG_REGNUM, ®_vg);
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return aarch64_sve_set_vq (tid, sve_vq_from_vg (reg_vg));
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}
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/* See nat/aarch64-sve-linux-ptrace.h. */
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std::unique_ptr<gdb_byte[]>
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aarch64_sve_get_sveregs (int tid)
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{
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struct iovec iovec;
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uint64_t vq = aarch64_sve_get_vq (tid);
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if (vq == 0)
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perror_with_name (_("Unable to fetch SVE register header"));
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/* A ptrace call with NT_ARM_SVE will return a header followed by either a
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dump of all the SVE and FP registers, or an fpsimd structure (identical to
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the one returned by NT_FPREGSET) if the kernel has not yet executed any
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SVE code. Make sure we allocate enough space for a full SVE dump. */
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iovec.iov_len = SVE_PT_SIZE (vq, SVE_PT_REGS_SVE);
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std::unique_ptr<gdb_byte[]> buf (new gdb_byte[iovec.iov_len]);
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iovec.iov_base = buf.get ();
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if (ptrace (PTRACE_GETREGSET, tid, NT_ARM_SVE, &iovec) < 0)
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perror_with_name (_("Unable to fetch SVE registers"));
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return buf;
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}
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/* If we are running in BE mode, byteswap the contents
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of SRC to DST for SIZE bytes. Other, just copy the contents
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from SRC to DST. */
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static void
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aarch64_maybe_swab128 (gdb_byte *dst, const gdb_byte *src, size_t size)
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{
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gdb_assert (src != nullptr && dst != nullptr);
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gdb_assert (size > 1);
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#if (__BYTE_ORDER == __BIG_ENDIAN)
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for (int i = 0; i < size - 1; i++)
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dst[i] = src[size - i];
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#else
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memcpy (dst, src, size);
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#endif
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}
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/* See nat/aarch64-sve-linux-ptrace.h. */
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void
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aarch64_sve_regs_copy_to_reg_buf (struct reg_buffer_common *reg_buf,
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const void *buf)
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{
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char *base = (char *) buf;
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struct user_sve_header *header = (struct user_sve_header *) buf;
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uint64_t vq = sve_vq_from_vl (header->vl);
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uint64_t vg = sve_vg_from_vl (header->vl);
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/* Sanity check the data in the header. */
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if (!sve_vl_valid (header->vl)
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|| SVE_PT_SIZE (vq, header->flags) != header->size)
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error (_("Invalid SVE header from kernel."));
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/* Update VG. Note, the registers in the regcache will already be of the
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correct length. */
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reg_buf->raw_supply (AARCH64_SVE_VG_REGNUM, &vg);
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if (HAS_SVE_STATE (*header))
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{
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/* The register dump contains a set of SVE registers. */
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for (int i = 0; i < AARCH64_SVE_Z_REGS_NUM; i++)
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reg_buf->raw_supply (AARCH64_SVE_Z0_REGNUM + i,
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base + SVE_PT_SVE_ZREG_OFFSET (vq, i));
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for (int i = 0; i < AARCH64_SVE_P_REGS_NUM; i++)
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reg_buf->raw_supply (AARCH64_SVE_P0_REGNUM + i,
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base + SVE_PT_SVE_PREG_OFFSET (vq, i));
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reg_buf->raw_supply (AARCH64_SVE_FFR_REGNUM,
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base + SVE_PT_SVE_FFR_OFFSET (vq));
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reg_buf->raw_supply (AARCH64_FPSR_REGNUM,
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base + SVE_PT_SVE_FPSR_OFFSET (vq));
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reg_buf->raw_supply (AARCH64_FPCR_REGNUM,
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base + SVE_PT_SVE_FPCR_OFFSET (vq));
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}
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else
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{
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/* WARNING: SIMD state is laid out in memory in target-endian format,
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while SVE state is laid out in an endianness-independent format (LE).
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So we have a couple cases to consider:
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1 - If the target is big endian, then SIMD state is big endian,
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requiring a byteswap.
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2 - If the target is little endian, then SIMD state is little endian,
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which matches the SVE format, so no byteswap is needed. */
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/* There is no SVE state yet - the register dump contains a fpsimd
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structure instead. These registers still exist in the hardware, but
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the kernel has not yet initialised them, and so they will be null. */
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gdb_byte *reg = (gdb_byte *) alloca (SVE_PT_SVE_ZREG_SIZE (vq));
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struct user_fpsimd_state *fpsimd
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= (struct user_fpsimd_state *)(base + SVE_PT_FPSIMD_OFFSET);
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/* Make sure we have a zeroed register buffer. We will need the zero
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padding below. */
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memset (reg, 0, SVE_PT_SVE_ZREG_SIZE (vq));
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/* Copy across the V registers from fpsimd structure to the Z registers,
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ensuring the non overlapping state is set to null. */
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for (int i = 0; i < AARCH64_SVE_Z_REGS_NUM; i++)
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{
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/* Handle big endian/little endian SIMD/SVE conversion. */
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aarch64_maybe_swab128 (reg, (const gdb_byte *) &fpsimd->vregs[i],
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V_REGISTER_SIZE);
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reg_buf->raw_supply (AARCH64_SVE_Z0_REGNUM + i, reg);
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}
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reg_buf->raw_supply (AARCH64_FPSR_REGNUM, &fpsimd->fpsr);
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reg_buf->raw_supply (AARCH64_FPCR_REGNUM, &fpsimd->fpcr);
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/* Clear the SVE only registers. */
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memset (reg, 0, SVE_PT_SVE_ZREG_SIZE (vq));
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for (int i = 0; i < AARCH64_SVE_P_REGS_NUM; i++)
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reg_buf->raw_supply (AARCH64_SVE_P0_REGNUM + i, reg);
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reg_buf->raw_supply (AARCH64_SVE_FFR_REGNUM, reg);
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}
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}
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/* See nat/aarch64-sve-linux-ptrace.h. */
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void
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aarch64_sve_regs_copy_from_reg_buf (const struct reg_buffer_common *reg_buf,
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void *buf)
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{
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struct user_sve_header *header = (struct user_sve_header *) buf;
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char *base = (char *) buf;
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uint64_t vq = sve_vq_from_vl (header->vl);
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/* Sanity check the data in the header. */
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if (!sve_vl_valid (header->vl)
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|| SVE_PT_SIZE (vq, header->flags) != header->size)
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error (_("Invalid SVE header from kernel."));
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if (!HAS_SVE_STATE (*header))
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{
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/* There is no SVE state yet - the register dump contains a fpsimd
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structure instead. Where possible we want to write the reg_buf data
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back to the kernel using the fpsimd structure. However, if we cannot
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then we'll need to reformat the fpsimd into a full SVE structure,
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resulting in the initialization of SVE state written back to the
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kernel, which is why we try to avoid it. */
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bool has_sve_state = false;
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gdb_byte *reg = (gdb_byte *) alloca (SVE_PT_SVE_ZREG_SIZE (vq));
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struct user_fpsimd_state *fpsimd
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= (struct user_fpsimd_state *)(base + SVE_PT_FPSIMD_OFFSET);
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memset (reg, 0, SVE_PT_SVE_ZREG_SIZE (vq));
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/* Check in the reg_buf if any of the Z registers are set after the
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first 128 bits, or if any of the other SVE registers are set. */
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for (int i = 0; i < AARCH64_SVE_Z_REGS_NUM; i++)
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{
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has_sve_state |= reg_buf->raw_compare (AARCH64_SVE_Z0_REGNUM + i,
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reg, sizeof (__int128_t));
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if (has_sve_state)
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break;
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}
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if (!has_sve_state)
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for (int i = 0; i < AARCH64_SVE_P_REGS_NUM; i++)
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{
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has_sve_state |= reg_buf->raw_compare (AARCH64_SVE_P0_REGNUM + i,
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reg, 0);
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if (has_sve_state)
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break;
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}
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if (!has_sve_state)
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has_sve_state |= reg_buf->raw_compare (AARCH64_SVE_FFR_REGNUM,
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reg, 0);
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/* If no SVE state exists, then use the existing fpsimd structure to
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write out state and return. */
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if (!has_sve_state)
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{
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/* WARNING: SIMD state is laid out in memory in target-endian format,
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while SVE state is laid out in an endianness-independent format
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(LE).
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So we have a couple cases to consider:
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1 - If the target is big endian, then SIMD state is big endian,
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requiring a byteswap.
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2 - If the target is little endian, then SIMD state is little
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endian, which matches the SVE format, so no byteswap is needed. */
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/* The collects of the Z registers will overflow the size of a vreg.
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There is enough space in the structure to allow for this, but we
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cannot overflow into the next register as we might not be
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collecting every register. */
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for (int i = 0; i < AARCH64_SVE_Z_REGS_NUM; i++)
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{
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if (REG_VALID
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== reg_buf->get_register_status (AARCH64_SVE_Z0_REGNUM + i))
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{
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reg_buf->raw_collect (AARCH64_SVE_Z0_REGNUM + i, reg);
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/* Handle big endian/little endian SIMD/SVE conversion. */
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aarch64_maybe_swab128 ((gdb_byte *) &fpsimd->vregs[i], reg,
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V_REGISTER_SIZE);
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}
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}
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if (REG_VALID == reg_buf->get_register_status (AARCH64_FPSR_REGNUM))
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reg_buf->raw_collect (AARCH64_FPSR_REGNUM, &fpsimd->fpsr);
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if (REG_VALID == reg_buf->get_register_status (AARCH64_FPCR_REGNUM))
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reg_buf->raw_collect (AARCH64_FPCR_REGNUM, &fpsimd->fpcr);
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return;
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}
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/* Otherwise, reformat the fpsimd structure into a full SVE set, by
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expanding the V registers (working backwards so we don't splat
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registers before they are copied) and using null for everything else.
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Note that enough space for a full SVE dump was originally allocated
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for base. */
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header->flags |= SVE_PT_REGS_SVE;
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header->size = SVE_PT_SIZE (vq, SVE_PT_REGS_SVE);
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memcpy (base + SVE_PT_SVE_FPSR_OFFSET (vq), &fpsimd->fpsr,
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sizeof (uint32_t));
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memcpy (base + SVE_PT_SVE_FPCR_OFFSET (vq), &fpsimd->fpcr,
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sizeof (uint32_t));
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for (int i = AARCH64_SVE_Z_REGS_NUM; i >= 0 ; i--)
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{
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memcpy (base + SVE_PT_SVE_ZREG_OFFSET (vq, i), &fpsimd->vregs[i],
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sizeof (__int128_t));
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}
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}
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/* Replace the kernel values with those from reg_buf. */
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for (int i = 0; i < AARCH64_SVE_Z_REGS_NUM; i++)
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if (REG_VALID == reg_buf->get_register_status (AARCH64_SVE_Z0_REGNUM + i))
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reg_buf->raw_collect (AARCH64_SVE_Z0_REGNUM + i,
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base + SVE_PT_SVE_ZREG_OFFSET (vq, i));
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for (int i = 0; i < AARCH64_SVE_P_REGS_NUM; i++)
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if (REG_VALID == reg_buf->get_register_status (AARCH64_SVE_P0_REGNUM + i))
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reg_buf->raw_collect (AARCH64_SVE_P0_REGNUM + i,
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base + SVE_PT_SVE_PREG_OFFSET (vq, i));
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if (REG_VALID == reg_buf->get_register_status (AARCH64_SVE_FFR_REGNUM))
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reg_buf->raw_collect (AARCH64_SVE_FFR_REGNUM,
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base + SVE_PT_SVE_FFR_OFFSET (vq));
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if (REG_VALID == reg_buf->get_register_status (AARCH64_FPSR_REGNUM))
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reg_buf->raw_collect (AARCH64_FPSR_REGNUM,
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base + SVE_PT_SVE_FPSR_OFFSET (vq));
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if (REG_VALID == reg_buf->get_register_status (AARCH64_FPCR_REGNUM))
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reg_buf->raw_collect (AARCH64_FPCR_REGNUM,
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base + SVE_PT_SVE_FPCR_OFFSET (vq));
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}
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