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789 lines
19 KiB
C
789 lines
19 KiB
C
/* Disassemble V850 instructions.
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Copyright 1996-2013 Free Software Foundation, Inc.
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This file is part of the GNU opcodes library.
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This library is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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It is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
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MA 02110-1301, USA. */
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#include "sysdep.h"
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#include <stdio.h>
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#include <string.h>
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#include "opcode/v850.h"
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#include "dis-asm.h"
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#include "opintl.h"
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static const char *const v850_reg_names[] =
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{
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"r0", "r1", "r2", "sp", "gp", "r5", "r6", "r7",
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"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
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"r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
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"r24", "r25", "r26", "r27", "r28", "r29", "ep", "lp"
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};
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static const char *const v850_sreg_names[] =
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{
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"eipc/vip/mpm", "eipsw/mpc", "fepc/tid", "fepsw/ppa", "ecr/vmecr", "psw/vmtid",
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"sr6/fpsr/vmadr/dcc", "sr7/fpepc/dc0",
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"sr8/fpst/vpecr/dcv1", "sr9/fpcc/vptid", "sr10/fpcfg/vpadr/spal", "sr11/spau",
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"sr12/vdecr/ipa0l", "eiic/vdtid/ipa0u", "feic/ipa1l", "dbic/ipa1u",
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"ctpc/ipa2l", "ctpsw/ipa2u", "dbpc/ipa3l", "dbpsw/ipa3u", "ctbp/dpa0l",
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"dir/dpa0u", "bpc/dpa0u", "asid/dpa1l",
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"bpav/dpa1u", "bpam/dpa2l", "bpdv/dpa2u", "bpdm/dpa3l", "eiwr/dpa3u",
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"fewr", "dbwr", "bsel"
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};
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static const char *const v850_cc_names[] =
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{
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"v", "c/l", "z", "nh", "s/n", "t", "lt", "le",
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"nv", "nc/nl", "nz", "h", "ns/p", "sa", "ge", "gt"
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};
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static const char *const v850_float_cc_names[] =
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{
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"f/t", "un/or", "eq/neq", "ueq/ogl", "olt/uge", "ult/oge", "ole/ugt", "ule/ogt",
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"sf/st", "ngle/gle", "seq/sne", "ngl/gl", "lt/nlt", "nge/ge", "le/nle", "ngt/gt"
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};
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static const char *const v850_vreg_names[] =
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{
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"vr0", "vr1", "vr2", "vr3", "vr4", "vr5", "vr6", "vr7", "vr8", "vr9",
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"vr10", "vr11", "vr12", "vr13", "vr14", "vr15", "vr16", "vr17", "vr18",
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"vr19", "vr20", "vr21", "vr22", "vr23", "vr24", "vr25", "vr26", "vr27",
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"vr28", "vr29", "vr30", "vr31"
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};
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static const char *const v850_cacheop_names[] =
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{
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"chbii", "cibii", "cfali", "cisti", "cildi", "chbid", "chbiwbd",
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"chbwbd", "cibid", "cibiwbd", "cibwbd", "cfald", "cistd", "cildd"
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};
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static const int v850_cacheop_codes[] =
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{
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0x00, 0x20, 0x40, 0x60, 0x61, 0x04, 0x06,
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0x07, 0x24, 0x26, 0x27, 0x44, 0x64, 0x65, -1
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};
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static const char *const v850_prefop_names[] =
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{ "prefi", "prefd" };
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static const int v850_prefop_codes[] =
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{ 0x00, 0x04, -1};
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static void
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print_value (int flags,
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bfd_vma memaddr,
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struct disassemble_info *info,
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long value)
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{
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if (flags & V850_PCREL)
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{
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bfd_vma addr = value + memaddr;
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if (flags & V850_INVERSE_PCREL)
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addr = memaddr - value;
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info->print_address_func (addr, info);
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}
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else if (flags & V850_OPERAND_DISP)
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{
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if (flags & V850_OPERAND_SIGNED)
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{
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info->fprintf_func (info->stream, "%ld", value);
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}
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else
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{
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info->fprintf_func (info->stream, "%lu", value);
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}
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}
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else if ((flags & V850E_IMMEDIATE32)
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|| (flags & V850E_IMMEDIATE16HI))
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{
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info->fprintf_func (info->stream, "0x%lx", value);
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}
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else
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{
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if (flags & V850_OPERAND_SIGNED)
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{
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info->fprintf_func (info->stream, "%ld", value);
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}
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else
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{
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info->fprintf_func (info->stream, "%lu", value);
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}
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}
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}
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static long
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get_operand_value (const struct v850_operand *operand,
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unsigned long insn,
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int bytes_read,
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bfd_vma memaddr,
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struct disassemble_info * info,
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bfd_boolean noerror,
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int *invalid)
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{
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long value;
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bfd_byte buffer[4];
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if ((operand->flags & V850E_IMMEDIATE16)
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|| (operand->flags & V850E_IMMEDIATE16HI))
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{
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int status = info->read_memory_func (memaddr + bytes_read, buffer, 2, info);
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if (status == 0)
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{
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value = bfd_getl16 (buffer);
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if (operand->flags & V850E_IMMEDIATE16HI)
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value <<= 16;
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else if (value & 0x8000)
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value |= (-1L << 16);
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return value;
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}
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if (!noerror)
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info->memory_error_func (status, memaddr + bytes_read, info);
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return 0;
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}
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if (operand->flags & V850E_IMMEDIATE23)
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{
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int status = info->read_memory_func (memaddr + 2, buffer, 4, info);
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if (status == 0)
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{
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value = bfd_getl32 (buffer);
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value = (operand->extract) (value, invalid);
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return value;
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}
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if (!noerror)
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info->memory_error_func (status, memaddr + bytes_read, info);
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return 0;
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}
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if (operand->flags & V850E_IMMEDIATE32)
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{
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int status = info->read_memory_func (memaddr + bytes_read, buffer, 4, info);
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if (status == 0)
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{
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bytes_read += 4;
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value = bfd_getl32 (buffer);
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return value;
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}
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if (!noerror)
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info->memory_error_func (status, memaddr + bytes_read, info);
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return 0;
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}
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if (operand->extract)
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value = (operand->extract) (insn, invalid);
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else
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{
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if (operand->bits == -1)
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value = (insn & operand->shift);
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else
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value = (insn >> operand->shift) & ((1 << operand->bits) - 1);
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if (operand->flags & V850_OPERAND_SIGNED)
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value = ((long)(value << (sizeof (long)*8 - operand->bits))
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>> (sizeof (long)*8 - operand->bits));
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}
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return value;
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}
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static int
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disassemble (bfd_vma memaddr,
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struct disassemble_info *info,
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int bytes_read,
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unsigned long insn)
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{
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struct v850_opcode *op = (struct v850_opcode *) v850_opcodes;
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const struct v850_operand *operand;
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int match = 0;
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int target_processor;
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switch (info->mach)
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{
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case 0:
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default:
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target_processor = PROCESSOR_V850;
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break;
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case bfd_mach_v850e:
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target_processor = PROCESSOR_V850E;
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break;
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case bfd_mach_v850e1:
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target_processor = PROCESSOR_V850E;
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break;
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case bfd_mach_v850e2:
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target_processor = PROCESSOR_V850E2;
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break;
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case bfd_mach_v850e2v3:
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target_processor = PROCESSOR_V850E2V3;
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break;
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case bfd_mach_v850e3v5:
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target_processor = PROCESSOR_V850E3V5;
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break;
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}
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/* If this is a two byte insn, then mask off the high bits. */
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if (bytes_read == 2)
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insn &= 0xffff;
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/* Find the opcode. */
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while (op->name)
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{
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if ((op->mask & insn) == op->opcode
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&& (op->processors & target_processor)
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&& !(op->processors & PROCESSOR_OPTION_ALIAS))
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{
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/* Code check start. */
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const unsigned char *opindex_ptr;
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unsigned int opnum;
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unsigned int memop;
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for (opindex_ptr = op->operands, opnum = 1;
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*opindex_ptr != 0;
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opindex_ptr++, opnum++)
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{
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int invalid = 0;
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long value;
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operand = &v850_operands[*opindex_ptr];
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value = get_operand_value (operand, insn, bytes_read, memaddr,
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info, 1, &invalid);
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if (invalid)
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goto next_opcode;
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if ((operand->flags & V850_NOT_R0) && value == 0 && (op->memop) <=2)
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goto next_opcode;
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if ((operand->flags & V850_NOT_SA) && value == 0xd)
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goto next_opcode;
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if ((operand->flags & V850_NOT_IMM0) && value == 0)
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goto next_opcode;
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}
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/* Code check end. */
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match = 1;
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(*info->fprintf_func) (info->stream, "%s\t", op->name);
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#if 0
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fprintf (stderr, "match: insn: %lx, mask: %lx, opcode: %lx, name: %s\n",
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insn, op->mask, op->opcode, op->name );
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#endif
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memop = op->memop;
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/* Now print the operands.
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MEMOP is the operand number at which a memory
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address specification starts, or zero if this
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instruction has no memory addresses.
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A memory address is always two arguments.
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This information allows us to determine when to
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insert commas into the output stream as well as
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when to insert disp[reg] expressions onto the
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output stream. */
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for (opindex_ptr = op->operands, opnum = 1;
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*opindex_ptr != 0;
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opindex_ptr++, opnum++)
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{
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bfd_boolean square = FALSE;
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long value;
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int flag;
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char *prefix;
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operand = &v850_operands[*opindex_ptr];
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value = get_operand_value (operand, insn, bytes_read, memaddr,
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info, 0, 0);
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/* The first operand is always output without any
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special handling.
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For the following arguments:
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If memop && opnum == memop + 1, then we need '[' since
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we're about to output the register used in a memory
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reference.
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If memop && opnum == memop + 2, then we need ']' since
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we just finished the register in a memory reference. We
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also need a ',' before this operand.
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Else we just need a comma.
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We may need to output a trailing ']' if the last operand
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in an instruction is the register for a memory address.
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The exception (and there's always an exception) are the
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"jmp" insn which needs square brackets around it's only
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register argument, and the clr1/not1/set1/tst1 insns
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which [...] around their second register argument. */
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prefix = "";
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if (operand->flags & V850_OPERAND_BANG)
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{
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prefix = "!";
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}
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else if (operand->flags & V850_OPERAND_PERCENT)
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{
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prefix = "%";
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}
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if (opnum == 1 && opnum == memop)
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{
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info->fprintf_func (info->stream, "%s[", prefix);
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square = TRUE;
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}
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else if ( (strcmp ("stc.w", op->name) == 0
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|| strcmp ("cache", op->name) == 0
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|| strcmp ("pref", op->name) == 0)
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&& opnum == 2 && opnum == memop)
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{
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info->fprintf_func (info->stream, ", [");
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square = TRUE;
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}
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else if ( (strcmp (op->name, "pushsp") == 0
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|| strcmp (op->name, "popsp") == 0
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|| strcmp (op->name, "dbpush" ) == 0)
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&& opnum == 2)
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{
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info->fprintf_func (info->stream, "-");
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}
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else if (opnum > 1
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&& (v850_operands[*(opindex_ptr - 1)].flags
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& V850_OPERAND_DISP) != 0
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&& opnum == memop)
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{
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info->fprintf_func (info->stream, "%s[", prefix);
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square = TRUE;
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}
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else if (opnum == 2
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&& ( op->opcode == 0x00e407e0 /* clr1 */
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|| op->opcode == 0x00e207e0 /* not1 */
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|| op->opcode == 0x00e007e0 /* set1 */
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|| op->opcode == 0x00e607e0 /* tst1 */
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))
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{
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info->fprintf_func (info->stream, ", %s[", prefix);
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square = TRUE;
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}
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else if (opnum > 1)
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info->fprintf_func (info->stream, ", %s", prefix);
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/* Extract the flags, ignoring ones which do not
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effect disassembly output. */
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flag = operand->flags & (V850_OPERAND_REG
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| V850_REG_EVEN
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| V850_OPERAND_EP
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| V850_OPERAND_SRG
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| V850E_OPERAND_REG_LIST
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| V850_OPERAND_CC
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| V850_OPERAND_VREG
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| V850_OPERAND_CACHEOP
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| V850_OPERAND_PREFOP
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| V850_OPERAND_FLOAT_CC);
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switch (flag)
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{
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case V850_OPERAND_REG:
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info->fprintf_func (info->stream, "%s", v850_reg_names[value]);
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break;
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case (V850_OPERAND_REG|V850_REG_EVEN):
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info->fprintf_func (info->stream, "%s", v850_reg_names[value * 2]);
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break;
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case V850_OPERAND_EP:
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info->fprintf_func (info->stream, "ep");
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break;
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case V850_OPERAND_SRG:
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info->fprintf_func (info->stream, "%s", v850_sreg_names[value]);
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break;
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case V850E_OPERAND_REG_LIST:
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{
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static int list12_regs[32] = { 30, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 31, 29, 28, 23, 22, 21, 20, 27, 26, 25, 24 };
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int *regs;
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int i;
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unsigned long int mask = 0;
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int pc = 0;
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switch (operand->shift)
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{
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case 0xffe00001: regs = list12_regs; break;
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default:
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/* xgettext:c-format */
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fprintf (stderr, _("unknown operand shift: %x\n"), operand->shift);
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abort ();
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}
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for (i = 0; i < 32; i++)
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{
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if (value & (1 << i))
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{
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switch (regs[ i ])
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{
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default: mask |= (1 << regs[ i ]); break;
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/* xgettext:c-format */
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case 0: fprintf (stderr, _("unknown reg: %d\n"), i ); abort ();
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case -1: pc = 1; break;
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}
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}
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}
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info->fprintf_func (info->stream, "{");
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if (mask || pc)
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{
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if (mask)
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{
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unsigned int bit;
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int shown_one = 0;
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for (bit = 0; bit < 32; bit++)
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if (mask & (1 << bit))
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{
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unsigned long int first = bit;
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unsigned long int last;
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if (shown_one)
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info->fprintf_func (info->stream, ", ");
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else
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shown_one = 1;
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info->fprintf_func (info->stream, "%s", v850_reg_names[first]);
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for (bit++; bit < 32; bit++)
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if ((mask & (1 << bit)) == 0)
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break;
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last = bit;
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if (last > first + 1)
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{
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info->fprintf_func (info->stream, " - %s", v850_reg_names[ last - 1 ]);
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}
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}
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}
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if (pc)
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info->fprintf_func (info->stream, "%sPC", mask ? ", " : "");
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}
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info->fprintf_func (info->stream, "}");
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}
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break;
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case V850_OPERAND_CC:
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info->fprintf_func (info->stream, "%s", v850_cc_names[value]);
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break;
|
|
|
|
case V850_OPERAND_FLOAT_CC:
|
|
info->fprintf_func (info->stream, "%s", v850_float_cc_names[value]);
|
|
break;
|
|
|
|
case V850_OPERAND_CACHEOP:
|
|
{
|
|
int idx;
|
|
|
|
for (idx = 0; v850_cacheop_codes[idx] != -1; idx++)
|
|
{
|
|
if (value == v850_cacheop_codes[idx])
|
|
{
|
|
info->fprintf_func (info->stream, "%s",
|
|
v850_cacheop_names[idx]);
|
|
goto MATCH_CACHEOP_CODE;
|
|
}
|
|
}
|
|
info->fprintf_func (info->stream, "%d", (int) value);
|
|
}
|
|
MATCH_CACHEOP_CODE:
|
|
break;
|
|
|
|
case V850_OPERAND_PREFOP:
|
|
{
|
|
int idx;
|
|
|
|
for (idx = 0; v850_prefop_codes[idx] != -1; idx++)
|
|
{
|
|
if (value == v850_prefop_codes[idx])
|
|
{
|
|
info->fprintf_func (info->stream, "%s",
|
|
v850_prefop_names[idx]);
|
|
goto MATCH_PREFOP_CODE;
|
|
}
|
|
}
|
|
info->fprintf_func (info->stream, "%d", (int) value);
|
|
}
|
|
MATCH_PREFOP_CODE:
|
|
break;
|
|
|
|
case V850_OPERAND_VREG:
|
|
info->fprintf_func (info->stream, "%s", v850_vreg_names[value]);
|
|
break;
|
|
|
|
default:
|
|
print_value (operand->flags, memaddr, info, value);
|
|
break;
|
|
}
|
|
|
|
if (square)
|
|
(*info->fprintf_func) (info->stream, "]");
|
|
}
|
|
|
|
/* All done. */
|
|
break;
|
|
}
|
|
next_opcode:
|
|
op++;
|
|
}
|
|
|
|
return match;
|
|
}
|
|
|
|
int
|
|
print_insn_v850 (bfd_vma memaddr, struct disassemble_info * info)
|
|
{
|
|
int status, status2, match;
|
|
bfd_byte buffer[8];
|
|
int length = 0, code_length = 0;
|
|
unsigned long insn = 0, insn2 = 0;
|
|
int target_processor;
|
|
|
|
switch (info->mach)
|
|
{
|
|
case 0:
|
|
default:
|
|
target_processor = PROCESSOR_V850;
|
|
break;
|
|
|
|
case bfd_mach_v850e:
|
|
target_processor = PROCESSOR_V850E;
|
|
break;
|
|
|
|
case bfd_mach_v850e1:
|
|
target_processor = PROCESSOR_V850E;
|
|
break;
|
|
|
|
case bfd_mach_v850e2:
|
|
target_processor = PROCESSOR_V850E2;
|
|
break;
|
|
|
|
case bfd_mach_v850e2v3:
|
|
target_processor = PROCESSOR_V850E2V3;
|
|
break;
|
|
|
|
case bfd_mach_v850e3v5:
|
|
target_processor = PROCESSOR_V850E3V5;
|
|
break;
|
|
}
|
|
|
|
status = info->read_memory_func (memaddr, buffer, 2, info);
|
|
|
|
if (status)
|
|
{
|
|
info->memory_error_func (status, memaddr, info);
|
|
return -1;
|
|
}
|
|
|
|
insn = bfd_getl16 (buffer);
|
|
|
|
status2 = info->read_memory_func (memaddr+2, buffer, 2 , info);
|
|
|
|
if (!status2)
|
|
{
|
|
insn2 = bfd_getl16 (buffer);
|
|
/* fprintf (stderr, "insn2 0x%08lx\n", insn2); */
|
|
}
|
|
|
|
/* Special case. */
|
|
if (length == 0
|
|
&& ((target_processor & PROCESSOR_V850E2_UP) != 0))
|
|
{
|
|
if ((insn & 0xffff) == 0x02e0 /* jr 32bit */
|
|
&& !status2 && (insn2 & 0x1) == 0)
|
|
{
|
|
length = 2;
|
|
code_length = 6;
|
|
}
|
|
else if ((insn & 0xffe0) == 0x02e0 /* jarl 32bit */
|
|
&& !status2 && (insn2 & 0x1) == 0)
|
|
{
|
|
length = 2;
|
|
code_length = 6;
|
|
}
|
|
else if ((insn & 0xffe0) == 0x06e0 /* jmp 32bit */
|
|
&& !status2 && (insn2 & 0x1) == 0)
|
|
{
|
|
length = 2;
|
|
code_length = 6;
|
|
}
|
|
}
|
|
|
|
if (length == 0
|
|
&& ((target_processor & PROCESSOR_V850E3V5_UP) != 0))
|
|
{
|
|
if ( ((insn & 0xffe0) == 0x07a0 /* ld.dw 23bit (v850e3v5) */
|
|
&& !status2 && (insn2 & 0x000f) == 0x0009)
|
|
|| ((insn & 0xffe0) == 0x07a0 /* st.dw 23bit (v850e3v5) */
|
|
&& !status2 && (insn2 & 0x000f) == 0x000f))
|
|
{
|
|
length = 4;
|
|
code_length = 6;
|
|
}
|
|
}
|
|
|
|
if (length == 0
|
|
&& ((target_processor & PROCESSOR_V850E2V3_UP) != 0))
|
|
{
|
|
if (((insn & 0xffe0) == 0x0780 /* ld.b 23bit */
|
|
&& !status2 && (insn2 & 0x000f) == 0x0005)
|
|
|| ((insn & 0xffe0) == 0x07a0 /* ld.bu 23bit */
|
|
&& !status2 && (insn2 & 0x000f) == 0x0005)
|
|
|| ((insn & 0xffe0) == 0x0780 /* ld.h 23bit */
|
|
&& !status2 && (insn2 & 0x000f) == 0x0007)
|
|
|| ((insn & 0xffe0) == 0x07a0 /* ld.hu 23bit */
|
|
&& !status2 && (insn2 & 0x000f) == 0x0007)
|
|
|| ((insn & 0xffe0) == 0x0780 /* ld.w 23bit */
|
|
&& !status2 && (insn2 & 0x000f) == 0x0009))
|
|
{
|
|
length = 4;
|
|
code_length = 6;
|
|
}
|
|
else if (((insn & 0xffe0) == 0x0780 /* st.b 23bit */
|
|
&& !status2 && (insn2 & 0x000f) == 0x000d)
|
|
|| ((insn & 0xffe0) == 0x07a0 /* st.h 23bit */
|
|
&& !status2 && (insn2 & 0x000f) == 0x000d)
|
|
|| ((insn & 0xffe0) == 0x0780 /* st.w 23bit */
|
|
&& !status2 && (insn2 & 0x000f) == 0x000f))
|
|
{
|
|
length = 4;
|
|
code_length = 6;
|
|
}
|
|
}
|
|
|
|
if (length == 0
|
|
&& target_processor != PROCESSOR_V850)
|
|
{
|
|
if ((insn & 0xffe0) == 0x0620) /* 32 bit MOV */
|
|
{
|
|
length = 2;
|
|
code_length = 6;
|
|
}
|
|
else if ((insn & 0xffc0) == 0x0780 /* prepare {list}, imm5, imm16<<16 */
|
|
&& !status2 && (insn2 & 0x001f) == 0x0013)
|
|
{
|
|
length = 4;
|
|
code_length = 6;
|
|
}
|
|
else if ((insn & 0xffc0) == 0x0780 /* prepare {list}, imm5, imm16 */
|
|
&& !status2 && (insn2 & 0x001f) == 0x000b)
|
|
{
|
|
length = 4;
|
|
code_length = 6;
|
|
}
|
|
else if ((insn & 0xffc0) == 0x0780 /* prepare {list}, imm5, imm32 */
|
|
&& !status2 && (insn2 & 0x001f) == 0x001b)
|
|
{
|
|
length = 4;
|
|
code_length = 8;
|
|
}
|
|
}
|
|
|
|
if (length == 4
|
|
|| (length == 0
|
|
&& (insn & 0x0600) == 0x0600))
|
|
{
|
|
/* This is a 4 byte insn. */
|
|
status = info->read_memory_func (memaddr, buffer, 4, info);
|
|
if (!status)
|
|
{
|
|
insn = bfd_getl32 (buffer);
|
|
|
|
if (!length)
|
|
length = code_length = 4;
|
|
}
|
|
}
|
|
|
|
if (code_length > length)
|
|
{
|
|
status = info->read_memory_func (memaddr + length, buffer, code_length - length, info);
|
|
if (status)
|
|
length = 0;
|
|
}
|
|
|
|
if (length == 0 && !status)
|
|
length = code_length = 2;
|
|
|
|
if (length == 2)
|
|
insn &= 0xffff;
|
|
|
|
/* when the last 2 bytes of section is 0xffff, length will be 0 and cause infinitive loop */
|
|
if (length == 0)
|
|
return -1;
|
|
|
|
match = disassemble (memaddr, info, length, insn);
|
|
|
|
if (!match)
|
|
{
|
|
int l = 0;
|
|
|
|
status = info->read_memory_func (memaddr, buffer, code_length, info);
|
|
|
|
while (l < code_length)
|
|
{
|
|
if (code_length - l == 2)
|
|
{
|
|
insn = bfd_getl16 (buffer + l) & 0xffff;
|
|
info->fprintf_func (info->stream, ".short\t0x%04lx", insn);
|
|
l += 2;
|
|
}
|
|
else
|
|
{
|
|
insn = bfd_getl32 (buffer + l);
|
|
info->fprintf_func (info->stream, ".long\t0x%08lx", insn);
|
|
l += 4;
|
|
}
|
|
}
|
|
}
|
|
|
|
return code_length;
|
|
}
|