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Spec: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html Contributors: Mary Bennett <mary.bennett@embecosm.com> Nandni Jamnadas <nandni.jamnadas@embecosm.com> Pietra Ferreira <pietra.ferreira@embecosm.com> Charlie Keaney Jessica Mills Craig Blackmore <craig.blackmore@embecosm.com> Simon Cook <simon.cook@embecosm.com> Jeremy Bennett <jeremy.bennett@embecosm.com> Helene Chelin <helene.chelin@embecosm.com> bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Added `xcvalu` instruction class. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * config/tc-riscv.c (validate_riscv_insn): Added the necessary operands for the extension. (riscv_ip): Likewise. * doc/c-riscv.texi: Noted XCValu as an additional ISA extension for CORE-V. * testsuite/gas/riscv/cv-alu-boundaries.d: New test. * testsuite/gas/riscv/cv-alu-boundaries.l: New test. * testsuite/gas/riscv/cv-alu-boundaries.s: New test. * testsuite/gas/riscv/cv-alu-fail-march.d: New test. * testsuite/gas/riscv/cv-alu-fail-march.l: New test. * testsuite/gas/riscv/cv-alu-fail-march.s: New test. * testsuite/gas/riscv/cv-alu-fail-operand-01.d: New test. * testsuite/gas/riscv/cv-alu-fail-operand-01.l: New test. * testsuite/gas/riscv/cv-alu-fail-operand-01.s: New test. * testsuite/gas/riscv/cv-alu-fail-operand-02.d: New test. * testsuite/gas/riscv/cv-alu-fail-operand-02.l: New test. * testsuite/gas/riscv/cv-alu-fail-operand-02.s: New test. * testsuite/gas/riscv/cv-alu-fail-operand-03.d: New test. * testsuite/gas/riscv/cv-alu-fail-operand-03.l: New test. * testsuite/gas/riscv/cv-alu-fail-operand-03.s: New test. * testsuite/gas/riscv/cv-alu-fail-operand-04.d: New test. * testsuite/gas/riscv/cv-alu-fail-operand-04.l: New test. * testsuite/gas/riscv/cv-alu-fail-operand-04.s: New test. * testsuite/gas/riscv/cv-alu-fail-operand-05.d: New test. * testsuite/gas/riscv/cv-alu-fail-operand-05.l: New test. * testsuite/gas/riscv/cv-alu-fail-operand-05.s: New test. * testsuite/gas/riscv/cv-alu-fail-operand-06.d: New test. * testsuite/gas/riscv/cv-alu-fail-operand-06.l: New test. * testsuite/gas/riscv/cv-alu-fail-operand-06.s: New test. * testsuite/gas/riscv/cv-alu-fail-operand-07.d: New test. * testsuite/gas/riscv/cv-alu-fail-operand-07.l: New test. * testsuite/gas/riscv/cv-alu-fail-operand-07.s: New test. * testsuite/gas/riscv/cv-alu-insns.d: New test. * testsuite/gas/riscv/cv-alu-insns.s: New test. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): Disassemble xcb operand. * riscv-opc.c: Defined the MASK and added XCValu instructions. include/ChangeLog: * opcode/riscv-opc.h: Added corresponding MATCH and MASK macros for XCValu. * opcode/riscv.h: Added corresponding EXTRACT and ENCODE macros for XCValu. (enum riscv_insn_class): Added the XCValu instruction class. |
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| aarch64.h | ||
| alpha.h | ||
| arc-attrs.h | ||
| arc-func.h | ||
| arc.h | ||
| arm.h | ||
| avr.h | ||
| bfin.h | ||
| bpf.h | ||
| cgen.h | ||
| ChangeLog-0415 | ||
| ChangeLog-9103 | ||
| convex.h | ||
| cr16.h | ||
| cris.h | ||
| crx.h | ||
| csky.h | ||
| d10v.h | ||
| d30v.h | ||
| dlx.h | ||
| ft32.h | ||
| h8300.h | ||
| hppa.h | ||
| i386.h | ||
| ia64.h | ||
| kvx.h | ||
| loongarch.h | ||
| m68hc11.h | ||
| m68k.h | ||
| metag.h | ||
| mips.h | ||
| mmix.h | ||
| mn10200.h | ||
| mn10300.h | ||
| moxie.h | ||
| msp430-decode.h | ||
| msp430.h | ||
| nds32.h | ||
| nfp.h | ||
| nios2.h | ||
| nios2r1.h | ||
| nios2r2.h | ||
| np1.h | ||
| ns32k.h | ||
| pdp11.h | ||
| pj.h | ||
| pn.h | ||
| ppc.h | ||
| pru.h | ||
| pyr.h | ||
| riscv-opc.h | ||
| riscv.h | ||
| rl78.h | ||
| rx.h | ||
| s12z.h | ||
| s390.h | ||
| score-datadep.h | ||
| score-inst.h | ||
| sparc.h | ||
| spu-insns.h | ||
| spu.h | ||
| tic4x.h | ||
| tic6x-control-registers.h | ||
| tic6x-insn-formats.h | ||
| tic6x-opcode-table.h | ||
| tic6x.h | ||
| tic30.h | ||
| tic54x.h | ||
| tilegx.h | ||
| tilepro.h | ||
| v850.h | ||
| vax.h | ||
| visium.h | ||
| wasm.h | ||
| xgate.h | ||