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b2e3f8442a
* Makefile.in: Added d30v object files. * configure: (bfd_d30v_arch) Rebuilt. * configure.in: (bfd_d30v_arch) Added new case. * d30v-dis.c: New file. * d30v-opc.c: New file. * disassemble.c (disassembler) Add entry for d30v.
415 lines
17 KiB
C
415 lines
17 KiB
C
/* d30v-opc.c -- D30V opcode list
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Copyright 1997 Free Software Foundation, Inc.
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Written by Martin Hunt, Cygnus Support
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This file is part of GDB, GAS, and the GNU binutils.
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GDB, GAS, and the GNU binutils are free software; you can redistribute
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them and/or modify them under the terms of the GNU General Public
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License as published by the Free Software Foundation; either version
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2, or (at your option) any later version.
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GDB, GAS, and the GNU binutils are distributed in the hope that they
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will be useful, but WITHOUT ANY WARRANTY; without even the implied
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warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
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the GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this file; see the file COPYING. If not, write to the Free
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Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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#include <stdio.h>
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#include "ansidecl.h"
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#include "opcode/d30v.h"
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/* This table is sorted. */
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/* If you add anything, it MUST be in alphabetical order */
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/* The first field is the name the assembler uses when looking */
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/* up orcodes. The second field is the name the disassembler will use. */
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/* This allows the assembler to assemble references to r63 (for example) */
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/* or "sp". The disassembler will always use the preferred form (sp) */
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const struct pd_reg pre_defined_registers[] =
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{
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{ "a0", NULL, OPERAND_ACC+0 },
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{ "a1", NULL, OPERAND_ACC+1 },
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{ "bpc", NULL, OPERAND_CONTROL+2 },
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{ "bpsw", NULL, OPERAND_CONTROL+3 },
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{ "c", "c", OPERAND_FLAG+7 },
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{ "cr0", "pc", OPERAND_CONTROL },
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{ "cr1", "psw", OPERAND_CONTROL+1 },
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{ "cr10", "mod_e", OPERAND_CONTROL+10 },
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{ "cr11", "iba", OPERAND_CONTROL+11 },
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{ "cr12", NULL, OPERAND_CONTROL+12 },
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{ "cr13", NULL, OPERAND_CONTROL+13 },
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{ "cr14", NULL, OPERAND_CONTROL+14 },
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{ "cr15", NULL, OPERAND_CONTROL+15 },
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{ "cr2", "bpc", OPERAND_CONTROL+2 },
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{ "cr3", "bpsw", OPERAND_CONTROL+3 },
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{ "cr4", NULL, OPERAND_CONTROL+4 },
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{ "cr5", NULL, OPERAND_CONTROL+5 },
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{ "cr6", "rpt_c", OPERAND_CONTROL+6 },
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{ "cr7", "rpt_s", OPERAND_CONTROL+7 },
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{ "cr8", "rpt_e", OPERAND_CONTROL+8 },
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{ "cr9", "mod_s", OPERAND_CONTROL+9 },
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{ "f0", NULL, OPERAND_FLAG+0 },
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{ "f1", NULL, OPERAND_FLAG+1 },
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{ "f2", NULL, OPERAND_FLAG+2 },
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{ "f3", NULL, OPERAND_FLAG+3 },
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{ "f4", "s", OPERAND_FLAG+4 },
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{ "f5", "v", OPERAND_FLAG+5 },
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{ "f6", "va", OPERAND_FLAG+6 },
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{ "f7", "c", OPERAND_FLAG+7 },
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{ "iba", NULL, OPERAND_CONTROL+11 },
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{ "link", "r62", 62 },
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{ "mod_e", NULL, OPERAND_CONTROL+10 },
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{ "mod_s", NULL, OPERAND_CONTROL+9 },
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{ "pc", NULL, OPERAND_CONTROL+0 },
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{ "psw", NULL, OPERAND_CONTROL+1 },
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{ "pswh", NULL, OPERAND_CONTROL+MAX_CONTROL_REG+2 },
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{ "pswl", NULL, OPERAND_CONTROL+MAX_CONTROL_REG+1 },
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{ "r0", "0", 0 },
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{ "r1", NULL, 1 },
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{ "r10", NULL, 10 },
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{ "r11", NULL, 11 },
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{ "r12", NULL, 12 },
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{ "r13", NULL, 13 },
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{ "r14", NULL, 14 },
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{ "r15", NULL, 15 },
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{ "r16", NULL, 16 },
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{ "r17", NULL, 17 },
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{ "r18", NULL, 18 },
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{ "r19", NULL, 19 },
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{ "r2", NULL, 2 },
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{ "r20", NULL, 20 },
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{ "r21", NULL, 21 },
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{ "r22", NULL, 22 },
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{ "r23", NULL, 23 },
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{ "r24", NULL, 24 },
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{ "r25", NULL, 25 },
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{ "r26", NULL, 26 },
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{ "r27", NULL, 27 },
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{ "r28", NULL, 28 },
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{ "r29", NULL, 29 },
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{ "r3", NULL, 3 },
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{ "r30", NULL, 30 },
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{ "r31", NULL, 31 },
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{ "r32", NULL, 32 },
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{ "r33", NULL, 33 },
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{ "r34", NULL, 34 },
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{ "r35", NULL, 35 },
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{ "r36", NULL, 36 },
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{ "r37", NULL, 37 },
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{ "r38", NULL, 38 },
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{ "r39", NULL, 39 },
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{ "r4", NULL, 4 },
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{ "r40", NULL, 40 },
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{ "r41", NULL, 41 },
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{ "r42", NULL, 42 },
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{ "r43", NULL, 43 },
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{ "r44", NULL, 44 },
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{ "r45", NULL, 45 },
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{ "r46", NULL, 46 },
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{ "r47", NULL, 47 },
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{ "r48", NULL, 48 },
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{ "r49", NULL, 49 },
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{ "r5", NULL, 5 },
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{ "r50", NULL, 50 },
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{ "r51", NULL, 51 },
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{ "r52", NULL, 52 },
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{ "r53", NULL, 53 },
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{ "r54", NULL, 54 },
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{ "r55", NULL, 55 },
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{ "r56", NULL, 56 },
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{ "r57", NULL, 57 },
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{ "r58", NULL, 58 },
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{ "r59", NULL, 59 },
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{ "r6", NULL, 6 },
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{ "r60", NULL, 60 },
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{ "r61", NULL, 61 },
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{ "r62", "link", 62 },
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{ "r63", "sp", 63 },
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{ "r7", NULL, 7 },
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{ "r8", NULL, 8 },
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{ "r9", NULL, 9 },
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{ "rpt_c", NULL, OPERAND_CONTROL+6 },
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{ "rpt_e", NULL, OPERAND_CONTROL+8 },
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{ "rpt_s", NULL, OPERAND_CONTROL+7 },
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{ "s", NULL, OPERAND_FLAG+4 },
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{ "sp", NULL, 63 },
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{ "v", NULL, OPERAND_FLAG+5 },
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{ "va", NULL, OPERAND_FLAG+6 },
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};
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int
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reg_name_cnt()
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{
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return (sizeof(pre_defined_registers) / sizeof(struct pd_reg));
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}
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/* OPCODE TABLE */
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/* The format of this table is defined in opcode/d30v.h */
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const struct d30v_opcode d30v_opcode_table[] = {
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{ "abs", IALU1, 0x8, { SHORT_U }, EITHER, 0, 0, 0 },
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{ "add", IALU1, 0x0, { SHORT_A, LONG}, EITHER, 0, FLAG_CVVA, 0 },
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{ "add2h", IALU1, 0x1, { SHORT_A, LONG}, EITHER, 0, 0, 0 },
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{ "addc", IALU1, 0x4, { SHORT_A, LONG }, EITHER, FLAG_C, FLAG_CVVA, 0 },
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{ "addhlll", IALU1, 0x10, { SHORT_A, LONG }, EITHER, 0, FLAG_CVVA, 0 },
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{ "addhllh", IALU1, 0x11, { SHORT_A, LONG }, EITHER, 0, FLAG_CVVA, 0 },
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{ "addhlhl", IALU1, 0x12, { SHORT_A, LONG }, EITHER, 0, FLAG_CVVA, 0 },
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{ "addhlhh", IALU1, 0x13, { SHORT_A, LONG }, EITHER, 0, FLAG_CVVA, 0 },
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{ "addhhll", IALU1, 0x14, { SHORT_A, LONG }, EITHER, 0, FLAG_CVVA, 0 },
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{ "addhhlh", IALU1, 0x15, { SHORT_A, LONG }, EITHER, 0, FLAG_CVVA, 0 },
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{ "addhhhl", IALU1, 0x16, { SHORT_A, LONG }, EITHER, 0, FLAG_CVVA, 0 },
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{ "addhhhh", IALU1, 0x17, { SHORT_A, LONG }, EITHER, 0, FLAG_CVVA, 0 },
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{ "adds", IALU1, 0x6, { SHORT_A, LONG }, EITHER, 0, FLAG_CVVA, 0 },
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{ "adds2h", IALU1, 0x7, { SHORT_A, LONG }, EITHER, 0, 0, 0 },
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{ "and", LOGIC, 0x18, { SHORT_A, LONG }, EITHER, 0, 0, 0 },
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{ "andfg", LOGIC, 0x8, { SHORT_F }, EITHER, FLAG_X, FLAG_X, 0 },
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{ "avg", IALU1, 0xa, { SHORT_A, LONG}, EITHER, 0, 0, 0 },
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{ "avg2h", IALU1, 0xb, { SHORT_A, LONG}, EITHER, 0, 0, 0 },
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{ "bclr", LOGIC, 0x3, { SHORT_A }, EITHER, 0, 0, 0 },
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{ "bnot", LOGIC, 0x1, { SHORT_A }, EITHER, 0, 0, 0 },
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{ "bra", BRA, 0, { SHORT_B1, SHORT_B2, LONG_U }, MU, FLAG_JMP, 0, RELOC_PCREL },
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{ "bratnz", BRA, 0x4, { SHORT_B3b, LONG_2b }, MU, FLAG_JMP, 0, RELOC_PCREL },
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{ "bratzr", BRA, 0x4, { SHORT_B3, LONG_2 }, MU, FLAG_JMP, 0, RELOC_PCREL },
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{ "bset", LOGIC, 0x2, { SHORT_A }, EITHER, 0, 0, 0 },
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{ "bsr", BRA, 0x2, { SHORT_B1, SHORT_B2, LONG_U }, MU, FLAG_JSR, 0, RELOC_PCREL },
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{ "bsrtnz", BRA, 0x6, { SHORT_B3b, LONG_2b }, MU, FLAG_JSR, 0, RELOC_PCREL },
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{ "bsrtzr", BRA, 0x6, { SHORT_B3, LONG_2 }, MU, FLAG_JSR, 0, RELOC_PCREL },
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{ "btst", LOGIC, 0, { SHORT_AF }, EITHER, 0, FLAG_X, 0 },
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{ "cmp", LOGIC, 0xC, { SHORT_CMP, LONG_CMP }, EITHER, 0, FLAG_X, 0 },
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{ "cmpu", LOGIC, 0xD, { SHORT_CMP, LONG_CMP }, EITHER, 0, FLAG_X, 0 },
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{ "dbra", BRA, 0x10, { SHORT_B3, LONG_2 }, MU, FLAG_JMP, FLAG_RP, RELOC_PCREL },
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{ "dbrai", BRA, 0x14, { SHORT_D2, LONG_D }, MU, FLAG_JMP, FLAG_RP, RELOC_PCREL },
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{ "dbsr", BRA, 0x12, { SHORT_B3, LONG_2 }, MU, FLAG_JSR, FLAG_RP, RELOC_PCREL },
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{ "dbsri", BRA, 0x16, { SHORT_D2, LONG_D }, MU, FLAG_JSR, FLAG_RP, RELOC_PCREL },
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{ "djmp", BRA, 0x11, { SHORT_B3, LONG_2 }, MU, FLAG_JMP, FLAG_RP, RELOC_ABS },
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{ "djmpi", BRA, 0x15, { SHORT_D2, LONG_D }, MU, FLAG_JMP, FLAG_RP, RELOC_ABS },
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{ "djsr", BRA, 0x13, { SHORT_B3, LONG_2 }, MU, FLAG_JSR, FLAG_RP, RELOC_ABS },
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{ "djsri", BRA, 0x17, { SHORT_D2, LONG_D }, MU, FLAG_JSR, FLAG_RP, RELOC_ABS },
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{ "jmp", BRA, 0x1, { SHORT_B1, SHORT_B2, LONG_U }, MU, FLAG_JMP, 0, RELOC_ABS },
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{ "jmptnz", BRA, 0x5, { SHORT_B3b, LONG_2b }, MU, FLAG_JMP, 0, RELOC_ABS },
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{ "jmptzr", BRA, 0x5, { SHORT_B3, LONG_2 }, MU, FLAG_JMP, 0, RELOC_ABS },
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{ "joinll", IALU1, 0xC, { SHORT_A, LONG }, EITHER, 0, 0, 0 },
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{ "joinlh", IALU1, 0xD, { SHORT_A, LONG }, EITHER, 0, 0, 0 },
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{ "joinhl", IALU1, 0xE, { SHORT_A, LONG }, EITHER, 0, 0, 0 },
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{ "joinhh", IALU1, 0xF, { SHORT_A, LONG }, EITHER, 0, 0, 0 },
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{ "jsr", BRA, 0x3, { SHORT_B1, SHORT_B2, LONG_U }, MU, FLAG_JSR, 0, RELOC_ABS },
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{ "jsrtnz", BRA, 0x7, { SHORT_B3b, LONG_2b }, MU, FLAG_JSR, 0, RELOC_ABS },
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{ "jsrtzr", BRA, 0x7, { SHORT_B3, LONG_2 }, MU, FLAG_JSR, 0, RELOC_ABS },
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{ "ld2h", IMEM, 0x3, { SHORT_M, LONG_M }, MU, FLAG_MEM, 0, 0 },
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{ "ld2w", IMEM, 0x6, { SHORT_M, LONG_M }, MU, FLAG_MEM, 0, 0 },
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{ "ld4bh", IMEM, 0x5, { SHORT_M, LONG_M }, MU, FLAG_MEM, 0, 0 },
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{ "ld4bhu", IMEM, 0xd, { SHORT_M, LONG_M }, MU, FLAG_MEM, 0, 0 },
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{ "ldb", IMEM, 0, { SHORT_M, LONG_M }, MU, FLAG_MEM, 0, 0 },
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{ "ldbu", IMEM, 0x9, { SHORT_M, LONG_M }, MU, FLAG_MEM, 0, 0 },
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{ "ldh", IMEM, 0x2, { SHORT_M, LONG_M }, MU, FLAG_MEM, 0, 0 },
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{ "ldhh", IMEM, 0x1, { SHORT_M, LONG_M }, MU, FLAG_MEM, 0, 0 },
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{ "ldhu", IMEM, 0xa, { SHORT_M, LONG_M }, MU, FLAG_MEM, 0, 0 },
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{ "ldw", IMEM, 0x4, { SHORT_M, LONG_M }, MU, FLAG_MEM, 0, 0 },
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{ "mac0", IALU2, 0x14, { SHORT_A }, IU, 0, 0, 0 },
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{ "mac1", IALU2, 0x14, { SHORT_A1 }, IU, 0, 0, 0 },
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{ "macs0", IALU2, 0x15, { SHORT_A }, IU, 0, 0, 0 },
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{ "macs1", IALU2, 0x15, { SHORT_A1 }, IU, 0, 0, 0 },
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{ "moddec", IMEM, 0x7, { SHORT_MODDEC }, MU, 0, 0, 0 },
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{ "modinc", IMEM, 0x7, { SHORT_MODINC }, MU, 0, 0, 0 },
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{ "msub0", IALU2, 0x16, { SHORT_A }, IU, 0, 0, 0 },
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{ "msub1", IALU2, 0x16, { SHORT_A1 }, IU, 0, 0, 0 },
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{ "msubs0", IALU2, 0x17, { SHORT_A }, IU, 0, 0, 0 },
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{ "msubs1", IALU2, 0x17, { SHORT_A1 }, IU, 0, 0, 0 },
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{ "mul", IALU2, 0x10, { SHORT_A }, IU, 0, 0, 0 },
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{ "mul2h", IALU2, 0, { SHORT_A }, IU, 0, 0, 0 },
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{ "mulhxll", IALU2, 0x4, { SHORT_A }, IU, 0, 0, 0 },
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{ "mulhxlh", IALU2, 0x5, { SHORT_A }, IU, 0, 0, 0 },
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{ "mulhxhl", IALU2, 0x6, { SHORT_A }, IU, 0, 0, 0 },
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{ "mulhxhh", IALU2, 0x7, { SHORT_A }, IU, 0, 0, 0 },
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{ "mulx", IALU2, 0x18, { SHORT_AA }, IU, 0, 0, 0 },
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{ "mulx2h", IALU2, 0x1, { SHORT_A }, IU, 0, 0, 0 },
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{ "mulxs", IALU2, 0x19, { SHORT_AA }, IU, 0, 0, 0 },
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{ "mvfacc", IALU2, 0x1f, { SHORT_RA }, IU, 0, 0, 0 },
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{ "mvfsys", BRA, 0x1e, { SHORT_C1 }, MU, FLAG_ALL, FLAG_ALL, 0 },
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{ "mvtacc", IALU2, 0xf, { SHORT_AA }, IU, 0, 0, 0 },
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{ "mvtsys", BRA, 0xe, { SHORT_C2 }, MU, FLAG_ALL, FLAG_ALL, 0 },
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{ "nop", BRA, 0xF, { SHORT_NONE }, EITHER, 0, 0, 0 },
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{ "not", LOGIC, 0x19, { SHORT_U }, EITHER, 0, 0, 0 },
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{ "notfg", LOGIC, 0x9, { SHORT_UF }, EITHER, FLAG_X, FLAG_X, 0 },
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{ "or", LOGIC, 0x1a, { SHORT_A, LONG }, EITHER, 0, 0, 0 },
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{ "orfg", LOGIC, 0xa, { SHORT_F }, EITHER, FLAG_X, FLAG_X, 0 },
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{ "reit", BRA, 0x8, { SHORT_NONE }, MU, FLAG_SM, FLAG_SM, 0 },
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{ "repeat", BRA, 0x18, { SHORT_D1, LONG_2 }, MU, FLAG_RP, FLAG_RP, 0 },
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{ "repeati", BRA, 0x1a, { SHORT_D2, LONG_D }, MU, FLAG_RP, FLAG_RP, 0 },
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{ "rot", LOGIC, 0x14, { SHORT_A }, EITHER, 0, 0, 0 },
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{ "rot2h", LOGIC, 0x15, { SHORT_A }, EITHER, 0, 0, 0 },
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{ "sat", IALU2, 0x8, { SHORT_A }, IU, 0, 0, 0 },
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{ "sat2h", IALU2, 0x9, { SHORT_A }, IU, 0, 0, 0 },
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{ "sathl", IALU2, 0x1c, { SHORT_A }, IU, 0, 0, 0 },
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{ "sathh", IALU2, 0x1d, { SHORT_A }, IU, 0, 0, 0 },
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{ "satz", IALU2, 0xa, { SHORT_A }, IU, 0, 0, 0 },
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{ "satz2h", IALU2, 0xb, { SHORT_A }, IU, 0, 0, 0 },
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{ "sra", LOGIC, 0x10, { SHORT_A }, EITHER, 0, 0, 0 },
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{ "sra2h", LOGIC, 0x11, { SHORT_A }, EITHER, 0, 0, 0 },
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{ "src", LOGIC, 0x16, { SHORT_A }, EITHER, 0, 0, 0 },
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{ "srl", LOGIC, 0x12, { SHORT_A }, EITHER, 0, 0, 0 },
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{ "srl2h", LOGIC, 0x12, { SHORT_A }, EITHER, 0, 0, 0 },
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{ "st2h", IMEM, 0x13, { SHORT_M, LONG_M }, MU, 0, FLAG_MEM, 0 },
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{ "st2w", IMEM, 0x16, { SHORT_M, LONG_M }, MU, 0, FLAG_MEM, 0 },
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{ "st4hb", IMEM, 0x15, { SHORT_M, LONG_M }, MU, 0, FLAG_MEM, 0 },
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{ "stb", IMEM, 0x10, { SHORT_M, LONG_M }, MU, 0, FLAG_MEM, 0 },
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{ "sth", IMEM, 0x12, { SHORT_M, LONG_M }, MU, 0, FLAG_MEM, 0 },
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{ "sthh", IMEM, 0x11, { SHORT_M, LONG_M }, MU, 0, FLAG_MEM, 0 },
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{ "stw", IMEM, 0x14, { SHORT_M, LONG_M }, MU, 0, FLAG_MEM, 0 },
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{ "sub", IALU1, 0x2, { SHORT_A, LONG}, EITHER, 0, FLAG_CVVA, 0 },
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{ "sub2h", IALU1, 0x3, { SHORT_A, LONG}, EITHER, 0, 0, 0 },
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{ "subb", IALU1, 0x5, { SHORT_A, LONG}, EITHER, FLAG_C, FLAG_CVVA, 0 },
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{ "subhlll", IALU1, 0x18, { SHORT_A, LONG}, EITHER, 0, FLAG_CVVA, 0 },
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{ "subhllh", IALU1, 0x19, { SHORT_A, LONG}, EITHER, 0, FLAG_CVVA, 0 },
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{ "subhlhl", IALU1, 0x1a, { SHORT_A, LONG}, EITHER, 0, FLAG_CVVA, 0 },
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{ "subhlhh", IALU1, 0x1b, { SHORT_A, LONG}, EITHER, 0, FLAG_CVVA, 0 },
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{ "subhhll", IALU1, 0x1c, { SHORT_A, LONG}, EITHER, 0, FLAG_CVVA, 0 },
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{ "subhhlh", IALU1, 0x1d, { SHORT_A, LONG}, EITHER, 0, FLAG_CVVA, 0 },
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{ "subhhhl", IALU1, 0x1e, { SHORT_A, LONG}, EITHER, 0, FLAG_CVVA, 0 },
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{ "subhhhh", IALU1, 0x1f, { SHORT_A, LONG}, EITHER, 0, FLAG_CVVA, 0 },
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{ "trap", BRA, 0x9, { SHORT_B1, SHORT_T}, MU, 0, FLAG_SM, 0 },
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{ "xor", LOGIC, 0x1b, { SHORT_A, LONG }, EITHER, 0, 0, 0 },
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{ "xorfg", LOGIC, 0xb, { SHORT_F }, EITHER, FLAG_X, FLAG_X, 0 },
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{ NULL, 0, 0, { 0 }, 0, 0, 0, 0 },
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};
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/* now define the operand types */
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/* format is length, bits, position, flags */
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const struct d30v_operand d30v_operand_table[] =
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{
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#define UNUSED (0)
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{ 0, 0, 0, 0 },
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#define Ra (UNUSED + 1)
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{ 6, 6, 0, OPERAND_REG|OPERAND_DEST },
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#define Rb (Ra + 1)
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{ 6, 6, 6, OPERAND_REG },
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#define Rc (Rb + 1)
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{ 6, 6, 12, OPERAND_REG },
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#define Aa (Rc + 1)
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{ 6, 1, 0, OPERAND_ACC|OPERAND_REG|OPERAND_DEST },
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#define Ab (Aa + 1)
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{ 6, 1, 6, OPERAND_ACC|OPERAND_REG },
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#define IMM5 (Ab + 1)
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{ 6, 5, 12, OPERAND_NUM|OPERAND_SIGNED },
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#define IMM5S3 (IMM5 + 1)
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{ 6, 5, 12, OPERAND_NUM|OPERAND_SIGNED },
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#define IMM6 (IMM5S3 + 1)
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{ 6, 6, 12, OPERAND_NUM|OPERAND_SIGNED },
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#define IMM12 (IMM6 + 1)
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{ 12, 12, 6, OPERAND_NUM|OPERAND_SIGNED },
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#define IMM12S3 (IMM12 + 1)
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{ 12, 12, 6, OPERAND_NUM|OPERAND_SIGNED|OPERAND_SHIFT },
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#define IMM18S3 (IMM12S3 + 1)
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{ 18, 18, 12, OPERAND_NUM|OPERAND_SIGNED|OPERAND_SHIFT },
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#define IMM32 (IMM18S3 + 1)
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{ 32, 32, 0, OPERAND_NUM },
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#define Fa (IMM32 + 1)
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{ 6, 3, 0, OPERAND_REG | OPERAND_FLAG | OPERAND_DEST },
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#define Fb (Fa + 1)
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{ 6, 3, 6, OPERAND_REG | OPERAND_FLAG },
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#define Fc (Fb + 1)
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{ 6, 3, 12, OPERAND_REG | OPERAND_FLAG },
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#define ATSIGN (Fc + 1)
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{ 0, 0, 0, OPERAND_ATSIGN},
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#define ATPAR (ATSIGN + 1) /* "@(" */
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{ 0, 0, 0, OPERAND_ATPAR},
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#define PLUS (ATPAR + 1) /* postincrement */
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{ 0, 0, 0, OPERAND_PLUS},
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#define MINUS (PLUS + 1) /* postdecrement */
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{ 0, 0, 0, OPERAND_MINUS},
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#define ATMINUS (MINUS + 1) /* predecrement */
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{ 0, 0, 0, OPERAND_ATMINUS},
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#define Ca (ATMINUS + 1) /* control register */
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{ 6, 4, 0, OPERAND_REG|OPERAND_CONTROL|OPERAND_DEST},
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#define Cb (Ca + 1) /* control register */
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{ 6, 4, 6, OPERAND_REG|OPERAND_CONTROL},
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#define CC (Cb + 1) /* condition code (CMPcc and CMPUcc) */
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{ 3, 3, -3, OPERAND_NAME},
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#define Fa2 (CC + 1) /* flag register (CMPcc and CMPUcc) */
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{ 3, 3, 0, OPERAND_REG|OPERAND_FLAG|OPERAND_DEST},
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#define Fake (Fa2 + 1) /* place holder for "id" field in mvfsys and mvtsys */
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{ 6, 2, 12, OPERAND_SPECIAL},
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};
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/* now we need to define the instruction formats */
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const struct d30v_format d30v_format_table[] =
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{
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{ 0, 0, { 0 } },
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{ SHORT_M, 0, { Ra, ATPAR, Rb, Rc } }, /* Ra,@(Rb,Rc) */
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{ SHORT_M, 1, { Ra, ATPAR, Rb, PLUS, Rc } }, /* Ra,@(Rb+,Rc) */
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{ SHORT_M, 2, { Ra, ATPAR, Rb, IMM6 } }, /* Ra,@(Rb,imm6) */
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{ SHORT_M, 3, { Ra, ATPAR, Rb, MINUS, Rc } }, /* Ra,@(Rb-,Rc) */
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{ SHORT_A, 0, { Ra, Rb, Rc } }, /* Ra,Rb,Rc */
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{ SHORT_A, 2, { Ra, Rb, IMM6 } }, /* Ra,Rb,imm6 */
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{ SHORT_B1, 0, { Rc } }, /* Rc */
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{ SHORT_B2, 2, { IMM18S3 } }, /* imm18 */
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{ SHORT_B3, 0, { Ra, Rc } }, /* Ra,Rc */
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{ SHORT_B3, 2, { Ra, IMM12 } }, /* Ra,imm12 */
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{ SHORT_B3b, 1, { Ra, Rc } }, /* Ra,Rc */
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{ SHORT_B3b, 3, { Ra, IMM12 } }, /* Ra,imm12 */
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{ SHORT_D1, 0, { Ra, Rc } }, /* Ra,Rc */
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{ SHORT_D1, 2, { Ra, IMM12S3 } }, /* Ra,imm12s3 */
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{ SHORT_D2, 0, { IMM6, Rc } }, /* imm6,Rc */
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{ SHORT_D2, 2, { IMM6, IMM12S3 } }, /* imm6,imm12s3 */
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{ SHORT_U, 0, { Ra, Rb } }, /* Ra,Rb */
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{ SHORT_U, 2, { Ra, IMM12 } }, /* Ra,imm12 (repeat) */
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{ SHORT_F, 0, { Fa, Fb, Fc } }, /* Fa,Fb,Fc (orfg, xorfg) */
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{ SHORT_F, 2, { Fa, Fb, IMM6 } }, /* Fa,Fb,imm6 */
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{ SHORT_AF, 0, { Fa, Rb, Rc } }, /* Fa,Rb,Rc */
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{ SHORT_AF, 2, { Fa, Rb, IMM6 } }, /* Fa,Rb,imm6 */
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{ SHORT_T, 2, { IMM5S3 } }, /* imm5s3 (trap) */
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{ SHORT_A5, 2, { Ra, Rb, IMM5 } }, /* Ra,Rb,imm5 (sat*) */
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{ SHORT_CMP, 0, { CC, Fa2, Rb, Rc} }, /* CC Fa2,Rb,Rc */
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{ SHORT_CMP, 2, { CC, Fa2, Rb, IMM6} }, /* CC Fa2,Rb,imm6 */
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{ SHORT_A1, 1, { Ra, Rb, Rc } }, /* Ra,Rb,Rc for MAC where a=1 */
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{ SHORT_A1, 3, { Ra, Rb, IMM6 } }, /* Ra,Rb,imm6 for MAC where a=1 */
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{ SHORT_AA, 0, { Aa, Rb, Rc } }, /* Aa,Rb,Rc */
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{ SHORT_AA, 2, { Aa, Rb, IMM6 } }, /* Aa,Rb,imm6 */
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{ SHORT_RA, 0, { Ra, Ab, Rc } }, /* Ra,Ab,Rc */
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{ SHORT_RA, 2, { Ra, Ab, IMM5 } }, /* Ra,Ab,imm5 */
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{ SHORT_MODINC, 1, { Rb, IMM5 } }, /* Rb,imm5 (modinc) */
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{ SHORT_MODDEC, 3, { Rb, IMM5 } }, /* Rb,imm5 (moddec) */
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{ SHORT_C1, 2, { Ra, Cb, Fake } }, /* Ra,Cb (mvfsys) */
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{ SHORT_C2, 2, { Ca, Rb, Fake } }, /* Ca,Rb (mvtsys) */
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{ SHORT_UF, 0, { Fa, Fb } }, /* Fa,Fb (notfg) */
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{ SHORT_NONE, 0, { 0 } }, /* no operands (nop, reit) */
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{ LONG, 2, { Ra, Rb, IMM32 } }, /* Ra,Rb,imm32 */
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{ LONG_U, 2, { IMM32 } }, /* imm32 */
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{ LONG_AF, 2, { Fa, Rb, IMM32 } }, /* Fa,Rb,imm32 */
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{ LONG_CMP, 2, { CC, Fa2, Rb, IMM32} }, /* CC Fa2,Rb,imm32 */
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{ LONG_M, 2, { Ra, ATPAR, Rb, IMM32 } }, /* Ra,@(Rb,imm32) */
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{ LONG_2, 2, { Ra, IMM32 } }, /* Ra,imm32 */
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{ LONG_2b, 3, { Ra, IMM32 } }, /* Ra,imm32 */
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{ LONG_D, 2, { IMM6, IMM32 } }, /* imm6,imm32 */
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{ 0, 0, { 0 } },
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};
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const char *d30v_ecc_names[] =
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{
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"al",
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"tx",
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"fx",
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"xt",
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"xf",
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"tt",
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"tf",
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"res"
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};
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const char *d30v_cc_names[] =
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{
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"eq",
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"ne",
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"gt",
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"ge",
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"lt",
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"le",
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"ps",
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"ng",
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NULL
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};
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