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https://sourceware.org/git/binutils-gdb.git
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1368b914e9
Now that all port tests live under testsuite/sim/*/, and none live in testsuite/ directly, flatten the structure by moving all of the dirs under testsuite/sim/ to testsuite/ directly. We need to stop passing --tool to dejagnu so that it searches all dirs and not just ones that start with "sim". Since we have no other dirs in this tree, and no plans to add any, should be fine.
170 lines
3.5 KiB
ArmAsm
170 lines
3.5 KiB
ArmAsm
# mach: bfin
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#include "test.h"
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.include "testutils.inc"
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start
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// 0xfffffe371c
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r0 = 0;
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r1 = 0;
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r2 = 0;
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r3 = 0;
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r4 = 0;
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r5 = 0;
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r6 = 0;
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r7 = 0;
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a1 = a0 =0;
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astat = R0;
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R6.L = 0x8000;
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R5.H = 0x8000;
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// load acc with values;
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R0.L = 0xc062;
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R0.H = 0xffee;
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A0.w = R0;
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R0.L = 0xc52c;
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A0.x = R0;
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R0.L = 0x8d10;
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R0.H = 0x34c;
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A1.w = R0;
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R0.L = 0xe10c;
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A1.x = R0;
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// load regs with values;
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R0.L = 0xe844;
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R0.H = 0x4aba;
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R1.L = 0xa294;
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R1.H = 0x52ea;
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R2.L = 0xafda;
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R2.H = 0x5c32;
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// end load regs and acc;
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R0.H = (A1 = R5.L * R6.H), R0.L = (A0 += R5.L * R6.H) (FU);
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P0 = ASTAT;
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CHECKREG P0, (_VS|_V|_V_COPY);
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CHECKREG R0, 0xffff;
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R0 = A1.w
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CHECKREG R0, 0;
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R0 = A1.x
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CHECKREG R0, 0;
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R0 = A0.w
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CHECKREG R0, 0xffeec062;
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R0 = A0.x
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CHECKREG R0, 0x2c;
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P0 = ASTAT;
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CHECKREG P0, (_VS|_V|_V_COPY);
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R4 = R6 +|- R5 , R3 = R6 -|+ R5;
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CHECKREG R3, 0x80008000;
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CHECKREG R4, 0x80008000;
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P0 = ASTAT;
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CHECKREG P0, (_VS|_V|_V_COPY|_AN);
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A1 = R7.L * R2.L (M), A0 -= R7.L * R2.H (IS);
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P0 = ASTAT;
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CHECKREG P0, (_VS|_V|_V_COPY|_AN);
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R7.H = R1.H * R3.L (TFU);
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CHECKREG R7, 0x29750000;
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P0 = ASTAT;
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CHECKREG P0, (_VS|_AN);
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R7.H = ( A1 -= R2.L * R5.H ), A0 = R2.L * R5.H;
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CHECKREG R7, 0xafda0000;
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R0 = A1.w
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CHECKREG R0, 0xafda0000;
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R0 = A1.x
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CHECKREG R0, 0xffffffff;
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R0 = A0.w
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CHECKREG R0, 0x50260000;
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R0 = A0.x
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CHECKREG R0, 0x0;
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P0 = ASTAT;
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CHECKREG P0, (_VS|_AN);
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R3 = R7.L * R6.H, R2 = R7.L * R6.H (IS);
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CHECKREG R3, 0;
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CHECKREG R2, 0;
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P0 = ASTAT;
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CHECKREG P0, (_VS|_AN);
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R1.H = (A1 += R7.L * R4.H) (M), R1.L = (A0 = R7.H * R4.H) (FU);
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CHECKREG R1, 0xafda57ed;
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P0 = ASTAT;
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R0 = A1.w
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CHECKREG R0, 0xafda0000;
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R0 = A1.x
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CHECKREG R0, 0xffffffff;
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R0 = A0.w
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CHECKREG R0, 0x57ed0000;
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R0 = A0.x
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CHECKREG R0, 0x0;
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CHECKREG P0, (_VS|_AN);
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R3 = R6.H * R5.L (FU);
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CHECKREG R3, 0;
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P0 = ASTAT;
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CHECKREG P0, (_VS|_AN);
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R5.H = ( A1 += R3.L * R1.L ) (M), A0 -= R3.H * R1.H (ISS2);
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CHECKREG R5, 0x80000000;
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R0 = A1.w
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CHECKREG R0, 0xafda0000;
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R0 = A1.x
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CHECKREG R0, 0xffffffff;
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R0 = A0.w
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CHECKREG R0, 0x57ed0000;
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R0 = A0.x
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CHECKREG R0, 0x0;
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P0 = ASTAT;
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CHECKREG P0, (_VS|_V|_V_COPY|_AN);
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R3 = R3 +|- R5 , R6 = R3 -|+ R5 (CO);
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CHECKREG R3, 0x80000000;
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CHECKREG R6, 0x00008000;
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P0 = ASTAT;
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CHECKREG P0, (_VS|_V|_V_COPY|_AN|_AZ);
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R7 = ( A1 += R4.L * R1.L ) (M), R6 = ( A0 += R4.L * R1.H );
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R0 = A1.w
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CHECKREG R0, 0x83e38000;
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R0 = A1.x
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CHECKREG R0, 0xffffffff;
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R0 = A0.w
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CHECKREG R0, 0xa8130000;
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R0 = A0.x
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CHECKREG R0, 0x0;
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CHECKREG R6, 0x7fffffff
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CHECKREG R7, 0x83e38000
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P0 = ASTAT;
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CHECKREG P0, (_VS|_V|_V_COPY|_AN|_AZ);
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IF CC P2 = R1;
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R2.H = (A1 = R7.L * R5.H) (M), R2.L = (A0 = R7.L * R5.H) (ISS2);
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CHECKREG R2, 0x80007fff
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P0 = ASTAT;
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CHECKREG P0, (_VS|_V|_V_COPY|_AN|_AZ);
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R3.H = R4.H * R2.H, R3.L = R4.L * R2.L (T);
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CHECKREG R3, 0x7fff8001
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P0 = ASTAT;
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CHECKREG P0, (_VS|_V|_V_COPY|_AN|_AZ);
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R7 = ( A1 = R7.H * R1.H ) (M), A0 -= R7.H * R1.H (FU);
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CHECKREG R7, 0xaabe7c4e
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P0 = ASTAT;
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CHECKREG P0, (_VS|_AV0S|_AV0|_AN|_AZ);
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R0.H = R7.L * R4.H (M), R0.L = R7.L * R4.H (TFU);
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CHECKREG R0, 0x3e273e27
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P0 = ASTAT;
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CHECKREG P0, (_VS|_AV0S|_AV0|_AN|_AZ);
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R5 = ( A1 = R7.L * R7.L ), R4 = ( A0 -= R7.H * R7.H ) (ISS2);
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CHECKREG R5, 0x78b74f88
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CHECKREG R4, 0xc73635f8
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R0 = A1.w
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CHECKREG R0, 0x3c5ba7c4;
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R0 = A1.x
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CHECKREG R0, 0x0;
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R0 = A0.w
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CHECKREG R0, 0xe39b1afc;
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R0 = A0.x
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CHECKREG R0, 0xffffffff;
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R0 = ASTAT;
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CHECKREG r0, (_VS|_AV0S|_AZ|_AN);
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A0 = A0 >> 2;
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R0 = ASTAT;
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checkreg r0, (_VS|_AV0S);
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R0 = A0.x;
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DBGA (R0.L, 0x3f);
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R0 = A0.w;
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checkreg r0, 0xF8E6C6BF;
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pass
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