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dd69d29260
2003-05-03 Chris Demetriou <cgd@broadcom.com>
* compare_igen_models: Tweak attribution slightly.
[mips/ChangeLog]
2003-05-03 Chris Demetriou <cgd@broadcom.com>
* cp1.c: Tweak attribution slightly.
* cp1.h: Likewise.
* mdmx.c: Likewise.
* mdmx.igen: Likewise.
* mips3d.igen: Likewise.
* sb1.igen: Likewise.
84 lines
3.2 KiB
C
84 lines
3.2 KiB
C
/*> cp1.h <*/
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/* MIPS Simulator FPU (CoProcessor 1) definitions.
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Copyright (C) 1997, 1998, 2002 Free Software Foundation, Inc.
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Derived from sim-main.h contributed by Cygnus Solutions,
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modified substantially by Ed Satterthwaite of Broadcom Corporation
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(SiByte).
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This file is part of GDB, the GNU debugger.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2, or (at your option)
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any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License along
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with this program; if not, write to the Free Software Foundation, Inc.,
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59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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#ifndef CP1_H
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#define CP1_H
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/* See sim-main.h for allocation of registers FCR0 and FCR31 (FCSR)
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in CPU state (struct sim_cpu), and for FPU functions. */
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#define fcsr_FCC_mask (0xFE800000)
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#define fcsr_FCC_shift (23)
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#define fcsr_FCC_bit(cc) ((cc) == 0 ? 23 : (24 + (cc)))
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#define fcsr_FS (1 << 24) /* MIPS III onwards : Flush to Zero */
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#define fcsr_ZERO_mask (0x007C0000)
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#define fcsr_CAUSE_mask (0x0003F000)
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#define fcsr_CAUSE_shift (12)
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#define fcsr_ENABLES_mask (0x00000F80)
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#define fcsr_ENABLES_shift (7)
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#define fcsr_FLAGS_mask (0x0000007C)
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#define fcsr_FLAGS_shift (2)
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#define fcsr_RM_mask (0x00000003)
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#define fcsr_RM_shift (0)
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#define fenr_FS (0x00000004)
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/* Macros to update and retrieve the FCSR condition-code bits. This
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is complicated by the fact that there is a hole in the index range
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of the bits within the FCSR register. (Note that the number of bits
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visible depends on the ISA in use, but that is handled elsewhere.) */
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#define SETFCC(cc,v) \
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do { \
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(FCSR = ((FCSR & ~(1 << fcsr_FCC_bit(cc))) | ((v) << fcsr_FCC_bit(cc)))); \
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} while (0)
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#define GETFCC(cc) ((FCSR & (1 << fcsr_FCC_bit(cc))) != 0 ? 1 : 0)
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/* Read flush-to-zero bit (not right-justified). */
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#define GETFS() ((int)(FCSR & fcsr_FS))
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/* FCSR flag bits definitions and access macros. */
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#define IR 0 /* I: Inexact Result */
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#define UF 1 /* U: UnderFlow */
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#define OF 2 /* O: OverFlow */
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#define DZ 3 /* Z: Division by Zero */
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#define IO 4 /* V: Invalid Operation */
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#define UO 5 /* E: Unimplemented Operation (CAUSE field only) */
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#define FP_FLAGS(b) (1 << ((b) + fcsr_FLAGS_shift))
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#define FP_ENABLE(b) (1 << ((b) + fcsr_ENABLES_shift))
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#define FP_CAUSE(b) (1 << ((b) + fcsr_CAUSE_shift))
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/* Rounding mode bit definitions and access macros. */
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#define FP_RM_NEAREST 0 /* Round to nearest (Round). */
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#define FP_RM_TOZERO 1 /* Round to zero (Trunc). */
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#define FP_RM_TOPINF 2 /* Round to Plus infinity (Ceil). */
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#define FP_RM_TOMINF 3 /* Round to Minus infinity (Floor). */
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#define GETRM() ((FCSR >> fcsr_RM_shift) & fcsr_RM_mask)
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#endif /* CP1_H */
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