mirror of
https://sourceware.org/git/binutils-gdb.git
synced 2024-12-21 04:42:53 +08:00
9a23f96e91
In the TLS GD/LD to LE optimization, ld replaces a sequence like addi 3,2,x@got@tlsgd R_PPC64_GOT_TLSGD16 x bl __tls_get_addr(x@tlsgd) R_PPC64_TLSGD x R_PPC64_REL24 __tls_get_addr nop with addis 3,13,x@tprel@ha R_PPC64_TPREL16_HA x addi 3,3,x@tprel@l R_PPC64_TPREL16_LO x nop When the tprel offset is small, this can be further optimized to nop addi 3,13,x@tprel nop bfd/ * elf64-ppc.c (struct ppc_link_hash_table): Add do_tls_opt. (ppc64_elf_tls_optimize): Set it. (ppc64_elf_relocate_section): Nop addis on TPREL16_HA, and convert insn on TPREL16_LO and TPREL16_LO_DS relocs to use r13 when addis would add zero. * elf32-ppc.c (struct ppc_elf_link_hash_table): Add do_tls_opt. (ppc_elf_tls_optimize): Set it. (ppc_elf_relocate_section): Nop addis on TPREL16_HA, and convert insn on TPREL16_LO relocs to use r2 when addis would add zero. gold/ * powerpc.cc (Target_powerpc::Relocate::relocate): Nop addis on TPREL16_HA, and convert insn on TPREL16_LO and TPREL16_LO_DS relocs to use r2/r13 when addis would add zero. ld/ * testsuite/ld-powerpc/tls.s: Add calls with tls markers. * testsuite/ld-powerpc/tls32.s: Likewise. * testsuite/ld-powerpc/powerpc.exp: Run tls marker tests. * testsuite/ld-powerpc/tls.d: Adjust for TPREL16_HA/LO optimization. * testsuite/ld-powerpc/tlsexe.d: Likewise. * testsuite/ld-powerpc/tlsexetoc.d: Likewise. * testsuite/ld-powerpc/tlsld.d: Likewise. * testsuite/ld-powerpc/tlsmark.d: Likewise. * testsuite/ld-powerpc/tlsopt4.d: Likewise. * testsuite/ld-powerpc/tlstoc.d: Likewise.
54 lines
1.9 KiB
Makefile
54 lines
1.9 KiB
Makefile
#source: tls.s
|
|
#source: tlslib.s
|
|
#as: -a64
|
|
#ld:
|
|
#objdump: -dr
|
|
#target: powerpc64*-*-*
|
|
|
|
.*
|
|
|
|
Disassembly of section \.text:
|
|
|
|
0+100000e8 <\._start>:
|
|
.*: (60 00 00 00|00 00 00 60) nop
|
|
.*: (38 6d 90 78|78 90 6d 38) addi r3,r13,-28552
|
|
.*: (60 00 00 00|00 00 00 60) nop
|
|
.*: (60 00 00 00|00 00 00 60) nop
|
|
.*: (38 6d 10 00|00 10 6d 38) addi r3,r13,4096
|
|
.*: (60 00 00 00|00 00 00 60) nop
|
|
.*: (60 00 00 00|00 00 00 60) nop
|
|
.*: (38 6d 90 40|40 90 6d 38) addi r3,r13,-28608
|
|
.*: (60 00 00 00|00 00 00 60) nop
|
|
.*: (60 00 00 00|00 00 00 60) nop
|
|
.*: (38 6d 10 00|00 10 6d 38) addi r3,r13,4096
|
|
.*: (60 00 00 00|00 00 00 60) nop
|
|
.*: (39 23 80 48|48 80 23 39) addi r9,r3,-32696
|
|
.*: (3d 23 00 00|00 00 23 3d) addis r9,r3,0
|
|
.*: (81 49 80 50|50 80 49 81) lwz r10,-32688\(r9\)
|
|
.*: (e9 22 80 10|10 80 22 e9) ld r9,-32752\(r2\)
|
|
.*: (7d 49 18 2a|2a 18 49 7d) ldx r10,r9,r3
|
|
.*: (60 00 00 00|00 00 00 60) nop
|
|
.*: (a1 4d 90 60|60 90 4d a1) lhz r10,-28576\(r13\)
|
|
.*: (89 4d 90 68|68 90 4d 89) lbz r10,-28568\(r13\)
|
|
.*: (60 00 00 00|00 00 00 60) nop
|
|
.*: (99 4d 90 70|70 90 4d 99) stb r10,-28560\(r13\)
|
|
.*: (60 00 00 00|00 00 00 60) nop
|
|
.*: (38 6d 90 00|00 90 6d 38) addi r3,r13,-28672
|
|
.*: (60 00 00 00|00 00 00 60) nop
|
|
.*: (60 00 00 00|00 00 00 60) nop
|
|
.*: (38 6d 10 00|00 10 6d 38) addi r3,r13,4096
|
|
.*: (60 00 00 00|00 00 00 60) nop
|
|
.*: (f9 43 80 08|08 80 43 f9) std r10,-32760\(r3\)
|
|
.*: (3d 23 00 00|00 00 23 3d) addis r9,r3,0
|
|
.*: (91 49 80 10|10 80 49 91) stw r10,-32752\(r9\)
|
|
.*: (e9 22 80 08|08 80 22 e9) ld r9,-32760\(r2\)
|
|
.*: (7d 49 19 2a|2a 19 49 7d) stdx r10,r9,r3
|
|
.*: (60 00 00 00|00 00 00 60) nop
|
|
.*: (b1 4d 90 60|60 90 4d b1) sth r10,-28576\(r13\)
|
|
.*: (e9 4d 90 2a|2a 90 4d e9) lwa r10,-28632\(r13\)
|
|
.*: (60 00 00 00|00 00 00 60) nop
|
|
.*: (a9 4d 90 30|30 90 4d a9) lha r10,-28624\(r13\)
|
|
|
|
0+10000180 <\.__tls_get_addr>:
|
|
.*: (4e 80 00 20|20 00 80 4e) blr
|