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303 lines
8.4 KiB
C
303 lines
8.4 KiB
C
/* Blackfin Pin Interrupt (PINT) model
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Copyright (C) 2010-2018 Free Software Foundation, Inc.
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Contributed by Analog Devices, Inc. and Mike Frysinger.
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This file is part of simulators.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#include "config.h"
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#include "sim-main.h"
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#include "devices.h"
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#include "dv-bfin_pint.h"
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struct bfin_pint
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{
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bu32 base;
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/* Only accessed indirectly via the associated set/clear MMRs. */
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bu32 mask, edge, invert;
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/* Order after here is important -- matches hardware MMR layout. */
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bu32 mask_set;
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bu32 mask_clear;
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bu32 request;
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bu32 assign;
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bu32 edge_set;
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bu32 edge_clear;
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bu32 invert_set;
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bu32 invert_clear;
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bu32 pinstate;
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bu32 latch;
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};
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#define mmr_base() offsetof(struct bfin_pint, mask_set)
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#define mmr_offset(mmr) (offsetof(struct bfin_pint, mmr) - mmr_base())
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static const char * const mmr_names[] =
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{
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"PINT_MASK_SET", "PINT_MASK_CLEAR", "PINT_REQUEST", "PINT_ASSIGN",
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"PINT_EDGE_SET", "PINT_EDGE_CLEAR", "PINT_INVERT_SET",
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"PINT_INVERT_CLEAR", "PINT_PINSTATE", "PINT_LATCH",
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};
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#define mmr_name(off) mmr_names[(off) / 4]
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static unsigned
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bfin_pint_io_write_buffer (struct hw *me, const void *source, int space,
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address_word addr, unsigned nr_bytes)
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{
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struct bfin_pint *pint = hw_data (me);
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bu32 mmr_off;
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bu32 value;
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bu32 *valuep;
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/* Invalid access mode is higher priority than missing register. */
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/* XXX: The hardware allows 16 or 32 bit accesses ... */
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if (!dv_bfin_mmr_require_32 (me, addr, nr_bytes, true))
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return 0;
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if (nr_bytes == 4)
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value = dv_load_4 (source);
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else
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value = dv_load_2 (source);
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mmr_off = addr - pint->base;
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valuep = (void *)((unsigned long)pint + mmr_base() + mmr_off);
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HW_TRACE_WRITE ();
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switch (mmr_off)
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{
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case mmr_offset(request):
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case mmr_offset(assign):
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case mmr_offset(pinstate):
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case mmr_offset(latch):
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*valuep = value;
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break;
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case mmr_offset(mask_set):
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dv_w1c_4 (&pint->mask, value, -1);
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break;
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case mmr_offset(mask_clear):
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pint->mask |= value;
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break;
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case mmr_offset(edge_set):
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dv_w1c_4 (&pint->edge, value, -1);
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break;
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case mmr_offset(edge_clear):
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pint->edge |= value;
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break;
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case mmr_offset(invert_set):
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dv_w1c_4 (&pint->invert, value, -1);
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break;
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case mmr_offset(invert_clear):
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pint->invert |= value;
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break;
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default:
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dv_bfin_mmr_invalid (me, addr, nr_bytes, true);
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return 0;
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}
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#if 0
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/* If updating masks, make sure we send updated port info. */
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switch (mmr_off)
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{
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case mmr_offset(dir):
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case mmr_offset(data) ... mmr_offset(toggle):
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bfin_pint_forward_ouput (me, pint, data);
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break;
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case mmr_offset(maska) ... mmr_offset(maska_toggle):
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bfin_pint_forward_int (me, pint, pint->maska, 0);
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break;
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case mmr_offset(maskb) ... mmr_offset(maskb_toggle):
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bfin_pint_forward_int (me, pint, pint->maskb, 1);
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break;
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}
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#endif
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return nr_bytes;
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}
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static unsigned
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bfin_pint_io_read_buffer (struct hw *me, void *dest, int space,
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address_word addr, unsigned nr_bytes)
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{
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struct bfin_pint *pint = hw_data (me);
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bu32 mmr_off;
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bu32 *valuep;
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/* Invalid access mode is higher priority than missing register. */
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/* XXX: The hardware allows 16 or 32 bit accesses ... */
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if (!dv_bfin_mmr_require_32 (me, addr, nr_bytes, false))
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return 0;
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mmr_off = addr - pint->base;
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valuep = (void *)((unsigned long)pint + mmr_base() + mmr_off);
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HW_TRACE_READ ();
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switch (mmr_off)
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{
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case mmr_offset(request):
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case mmr_offset(assign):
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case mmr_offset(pinstate):
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case mmr_offset(latch):
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dv_store_4 (dest, *valuep);
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break;
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case mmr_offset(mask_set):
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case mmr_offset(mask_clear):
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dv_store_4 (dest, pint->mask);
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break;
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case mmr_offset(edge_set):
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case mmr_offset(edge_clear):
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dv_store_4 (dest, pint->edge);
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break;
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case mmr_offset(invert_set):
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case mmr_offset(invert_clear):
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dv_store_4 (dest, pint->invert);
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break;
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default:
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dv_bfin_mmr_invalid (me, addr, nr_bytes, false);
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return 0;
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}
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return nr_bytes;
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}
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#define ENC(bmap, piq) (((bmap) << 8) + (piq))
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#define PIQ_PORTS(n) \
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{ "piq0@"#n, ENC(n, 0), 0, input_port, }, \
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{ "piq1@"#n, ENC(n, 1), 0, input_port, }, \
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{ "piq2@"#n, ENC(n, 2), 0, input_port, }, \
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{ "piq3@"#n, ENC(n, 3), 0, input_port, }, \
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{ "piq4@"#n, ENC(n, 4), 0, input_port, }, \
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{ "piq5@"#n, ENC(n, 5), 0, input_port, }, \
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{ "piq6@"#n, ENC(n, 6), 0, input_port, }, \
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{ "piq7@"#n, ENC(n, 7), 0, input_port, }, \
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{ "piq8@"#n, ENC(n, 8), 0, input_port, }, \
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{ "piq9@"#n, ENC(n, 9), 0, input_port, }, \
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{ "piq10@"#n, ENC(n, 10), 0, input_port, }, \
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{ "piq11@"#n, ENC(n, 11), 0, input_port, }, \
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{ "piq12@"#n, ENC(n, 12), 0, input_port, }, \
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{ "piq13@"#n, ENC(n, 13), 0, input_port, }, \
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{ "piq14@"#n, ENC(n, 14), 0, input_port, }, \
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{ "piq15@"#n, ENC(n, 15), 0, input_port, }, \
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{ "piq16@"#n, ENC(n, 16), 0, input_port, }, \
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{ "piq17@"#n, ENC(n, 17), 0, input_port, }, \
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{ "piq18@"#n, ENC(n, 18), 0, input_port, }, \
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{ "piq19@"#n, ENC(n, 19), 0, input_port, }, \
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{ "piq20@"#n, ENC(n, 20), 0, input_port, }, \
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{ "piq21@"#n, ENC(n, 21), 0, input_port, }, \
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{ "piq22@"#n, ENC(n, 22), 0, input_port, }, \
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{ "piq23@"#n, ENC(n, 23), 0, input_port, }, \
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{ "piq24@"#n, ENC(n, 24), 0, input_port, }, \
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{ "piq25@"#n, ENC(n, 25), 0, input_port, }, \
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{ "piq26@"#n, ENC(n, 26), 0, input_port, }, \
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{ "piq27@"#n, ENC(n, 27), 0, input_port, }, \
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{ "piq28@"#n, ENC(n, 28), 0, input_port, }, \
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{ "piq29@"#n, ENC(n, 29), 0, input_port, }, \
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{ "piq30@"#n, ENC(n, 30), 0, input_port, }, \
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{ "piq31@"#n, ENC(n, 31), 0, input_port, },
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static const struct hw_port_descriptor bfin_pint_ports[] =
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{
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{ "stat", 0, 0, output_port, },
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PIQ_PORTS(0)
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PIQ_PORTS(1)
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PIQ_PORTS(2)
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PIQ_PORTS(3)
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PIQ_PORTS(4)
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PIQ_PORTS(5)
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PIQ_PORTS(6)
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PIQ_PORTS(7)
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{ NULL, 0, 0, 0, },
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};
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static void
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bfin_pint_port_event (struct hw *me, int my_port, struct hw *source,
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int source_port, int level)
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{
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/* XXX: TODO. */
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}
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static void
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attach_bfin_pint_regs (struct hw *me, struct bfin_pint *pint)
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{
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address_word attach_address;
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int attach_space;
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unsigned attach_size;
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reg_property_spec reg;
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if (hw_find_property (me, "reg") == NULL)
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hw_abort (me, "Missing \"reg\" property");
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if (!hw_find_reg_array_property (me, "reg", 0, ®))
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hw_abort (me, "\"reg\" property must contain three addr/size entries");
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hw_unit_address_to_attach_address (hw_parent (me),
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®.address,
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&attach_space, &attach_address, me);
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hw_unit_size_to_attach_size (hw_parent (me), ®.size, &attach_size, me);
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if (attach_size != BFIN_MMR_PINT_SIZE)
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hw_abort (me, "\"reg\" size must be %#x", BFIN_MMR_PINT_SIZE);
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hw_attach_address (hw_parent (me),
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0, attach_space, attach_address, attach_size, me);
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pint->base = attach_address;
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}
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static void
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bfin_pint_finish (struct hw *me)
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{
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struct bfin_pint *pint;
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pint = HW_ZALLOC (me, struct bfin_pint);
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set_hw_data (me, pint);
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set_hw_io_read_buffer (me, bfin_pint_io_read_buffer);
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set_hw_io_write_buffer (me, bfin_pint_io_write_buffer);
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set_hw_ports (me, bfin_pint_ports);
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set_hw_port_event (me, bfin_pint_port_event);
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/* Initialize the PINT. */
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switch (dv_get_bus_num (me))
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{
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case 0:
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pint->assign = 0x00000101;
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break;
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case 1:
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pint->assign = 0x01010000;
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break;
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case 2:
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pint->assign = 0x00000101;
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break;
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case 3:
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pint->assign = 0x02020303;
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break;
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default:
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/* XXX: Should move this default into device tree. */
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hw_abort (me, "no support for PINT at this address yet");
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}
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attach_bfin_pint_regs (me, pint);
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}
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const struct hw_descriptor dv_bfin_pint_descriptor[] =
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{
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{"bfin_pint", bfin_pint_finish,},
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{NULL, NULL},
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};
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