Mike Frysinger ce2486ab20 sim: bfin: pass up result2/errcode with libgloss syscalls ... Now that the Blackfin libgloss code extracts the 2nd result and the error code from the R1/R2 registers, have the sim fill them up. Signed-off-by: Mike Frysinger <vapier@gentoo.org>		2011-06-22 04:21:29 +00:00
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arm
avr
bfin	sim: bfin: pass up result2/errcode with libgloss syscalls	2011-06-22 04:21:29 +00:00
common
cr16
cris
d10v
erc32
frv
h8300
igen
iq2000
lm32
m32c
m32r
m68hc11
mcore
microblaze
mips
mn10300	* am33.igen (sub Rm,Rn,Rd): Fix computation of carry flag.	2011-06-20 16:50:51 +00:00
moxie
ppc
rx
sh
sh64
testsuite	sim: bfin: add tests for recent dsp fixes	2011-06-18 20:27:26 +00:00
v850
.gitignore
ChangeLog
configure
configure.ac
configure.tgt
MAINTAINERS
Makefile.in
README-HACKING