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ea3352172e
The current implementation of the fcc register is referenced to the
user_fp_state structure of the kernel uapi [1].
struct user_fp_state {
uint64_t fpr[32];
uint64_t fcc;
uint32_t fcsr;
};
But it is mistakenly defined as a 64-bit fputype register, resulting
in a confusing output of "info register".
(gdb) info register
...
fcc {f = 0x0, d = 0x0} {f = 0, d = 0}
...
According to "Condition Flag Register" in "LoongArch Reference Manual"
[2], there are 8 condition flag registers of size 1. Use 8 registers of
uint8 to make it easier for users to view the fcc register groups.
(gdb) info register
...
fcc0 0x1 1
fcc1 0x0 0
fcc2 0x0 0
fcc3 0x0 0
fcc4 0x0 0
fcc5 0x0 0
fcc6 0x0 0
fcc7 0x0 0
...
[1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/loongarch/include/uapi/asm/ptrace.h
[2] https://loongson.github.io/LoongArch-Documentation/LoongArch-Vol1-EN.html#_condition_flag_register
Signed-off-by: Feiyang Chen <chenfeiyang@loongson.cn>
Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn>
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| .. | ||
| aarch32.c | ||
| aarch32.h | ||
| aarch64-insn.c | ||
| aarch64-insn.h | ||
| aarch64-mte-linux.c | ||
| aarch64-mte-linux.h | ||
| aarch64.c | ||
| aarch64.h | ||
| amd64.c | ||
| amd64.h | ||
| arc.c | ||
| arc.h | ||
| arm-get-next-pcs.c | ||
| arm-get-next-pcs.h | ||
| arm-linux.c | ||
| arm-linux.h | ||
| arm.c | ||
| arm.h | ||
| i386.c | ||
| i386.h | ||
| loongarch.c | ||
| loongarch.h | ||
| ppc-linux-common.c | ||
| ppc-linux-common.h | ||
| ppc-linux-tdesc.h | ||
| riscv.c | ||
| riscv.h | ||
| tic6x.c | ||
| tic6x.h | ||
| xtensa.h | ||