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a2c5833233
The result of running etc/update-copyright.py --this-year, fixing all the files whose mode is changed by the script, plus a build with --enable-maintainer-mode --enable-cgen-maint=yes, then checking out */po/*.pot which we don't update frequently. The copy of cgen was with commit d1dd5fcc38ead reverted as that commit breaks building of bfp opcodes files.
346 lines
10 KiB
Plaintext
346 lines
10 KiB
Plaintext
@c Copyright (C) 1991-2022 Free Software Foundation, Inc.
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@c This is part of the GAS manual.
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@c For copying conditions, see the file as.texinfo.
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@page
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@node SH-Dependent
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@chapter Renesas / SuperH SH Dependent Features
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@cindex SH support
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@menu
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* SH Options:: Options
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* SH Syntax:: Syntax
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* SH Floating Point:: Floating Point
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* SH Directives:: SH Machine Directives
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* SH Opcodes:: Opcodes
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@end menu
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@node SH Options
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@section Options
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@cindex SH options
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@cindex options, SH
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@code{@value{AS}} has following command-line options for the Renesas
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(formerly Hitachi) / SuperH SH family.
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@table @code
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@kindex --little
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@kindex --big
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@kindex --relax
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@kindex --small
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@kindex --dsp
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@kindex --renesas
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@kindex --allow-reg-prefix
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@item --little
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Generate little endian code.
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@item --big
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Generate big endian code.
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@item --relax
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Alter jump instructions for long displacements.
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@item --small
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Align sections to 4 byte boundaries, not 16.
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@item --dsp
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Enable sh-dsp insns, and disable sh3e / sh4 insns.
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@item --renesas
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Disable optimization with section symbol for compatibility with
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Renesas assembler.
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@item --allow-reg-prefix
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Allow '$' as a register name prefix.
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@kindex --fdpic
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@item --fdpic
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Generate an FDPIC object file.
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@item --isa=sh4 | sh4a
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Specify the sh4 or sh4a instruction set.
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@item --isa=dsp
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Enable sh-dsp insns, and disable sh3e / sh4 insns.
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@item --isa=fp
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Enable sh2e, sh3e, sh4, and sh4a insn sets.
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@item --isa=all
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Enable sh1, sh2, sh2e, sh3, sh3e, sh4, sh4a, and sh-dsp insn sets.
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@item -h-tick-hex
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Support H'00 style hex constants in addition to 0x00 style.
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@end table
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@node SH Syntax
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@section Syntax
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@menu
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* SH-Chars:: Special Characters
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* SH-Regs:: Register Names
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* SH-Addressing:: Addressing Modes
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@end menu
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@node SH-Chars
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@subsection Special Characters
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@cindex line comment character, SH
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@cindex SH line comment character
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@samp{!} is the line comment character.
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@cindex line separator, SH
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@cindex statement separator, SH
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@cindex SH line separator
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You can use @samp{;} instead of a newline to separate statements.
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If a @samp{#} appears as the first character of a line then the whole
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line is treated as a comment, but in this case the line could also be
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a logical line number directive (@pxref{Comments}) or a preprocessor
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control command (@pxref{Preprocessing}).
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@cindex symbol names, @samp{$} in
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@cindex @code{$} in symbol names
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Since @samp{$} has no special meaning, you may use it in symbol names.
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@node SH-Regs
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@subsection Register Names
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@cindex SH registers
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@cindex registers, SH
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You can use the predefined symbols @samp{r0}, @samp{r1}, @samp{r2},
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@samp{r3}, @samp{r4}, @samp{r5}, @samp{r6}, @samp{r7}, @samp{r8},
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@samp{r9}, @samp{r10}, @samp{r11}, @samp{r12}, @samp{r13}, @samp{r14},
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and @samp{r15} to refer to the SH registers.
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The SH also has these control registers:
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@table @code
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@item pr
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procedure register (holds return address)
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@item pc
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program counter
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@item mach
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@itemx macl
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high and low multiply accumulator registers
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@item sr
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status register
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@item gbr
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global base register
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@item vbr
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vector base register (for interrupt vectors)
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@end table
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@node SH-Addressing
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@subsection Addressing Modes
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@cindex addressing modes, SH
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@cindex SH addressing modes
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@code{@value{AS}} understands the following addressing modes for the SH.
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@code{R@var{n}} in the following refers to any of the numbered
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registers, but @emph{not} the control registers.
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@table @code
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@item R@var{n}
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Register direct
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@item @@R@var{n}
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Register indirect
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@item @@-R@var{n}
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Register indirect with pre-decrement
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@item @@R@var{n}+
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Register indirect with post-increment
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@item @@(@var{disp}, R@var{n})
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Register indirect with displacement
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@item @@(R0, R@var{n})
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Register indexed
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@item @@(@var{disp}, GBR)
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@code{GBR} offset
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@item @@(R0, GBR)
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GBR indexed
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@item @var{addr}
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@itemx @@(@var{disp}, PC)
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PC relative address (for branch or for addressing memory). The
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@code{@value{AS}} implementation allows you to use the simpler form
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@var{addr} anywhere a PC relative address is called for; the alternate
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form is supported for compatibility with other assemblers.
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@item #@var{imm}
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Immediate data
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@end table
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@node SH Floating Point
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@section Floating Point
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@cindex floating point, SH (@sc{ieee})
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@cindex SH floating point (@sc{ieee})
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SH2E, SH3E and SH4 groups have on-chip floating-point unit (FPU). Other
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SH groups can use @code{.float} directive to generate @sc{ieee}
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floating-point numbers.
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SH2E and SH3E support single-precision floating point calculations as
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well as entirely PCAPI compatible emulation of double-precision
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floating point calculations. SH2E and SH3E instructions are a subset of
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the floating point calculations conforming to the IEEE754 standard.
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In addition to single-precision and double-precision floating-point
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operation capability, the on-chip FPU of SH4 has a 128-bit graphic
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engine that enables 32-bit floating-point data to be processed 128
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bits at a time. It also supports 4 * 4 array operations and inner
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product operations. Also, a superscalar architecture is employed that
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enables simultaneous execution of two instructions (including FPU
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instructions), providing performance of up to twice that of
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conventional architectures at the same frequency.
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@node SH Directives
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@section SH Machine Directives
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@cindex SH machine directives
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@cindex machine directives, SH
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@cindex @code{uaword} directive, SH
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@cindex @code{ualong} directive, SH
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@cindex @code{uaquad} directive, SH
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@table @code
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@item uaword
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@itemx ualong
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@itemx uaquad
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@code{@value{AS}} will issue a warning when a misaligned @code{.word},
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@code{.long}, or @code{.quad} directive is used. You may use
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@code{.uaword}, @code{.ualong}, or @code{.uaquad} to indicate that the
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value is intentionally misaligned.
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@end table
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@node SH Opcodes
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@section Opcodes
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@cindex SH opcode summary
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@cindex opcode summary, SH
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@cindex mnemonics, SH
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@cindex instruction summary, SH
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For detailed information on the SH machine instruction set, see
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@cite{SH-Microcomputer User's Manual} (Renesas) or
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@cite{SH-4 32-bit CPU Core Architecture} (SuperH) and
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@cite{SuperH (SH) 64-Bit RISC Series} (SuperH).
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@code{@value{AS}} implements all the standard SH opcodes. No additional
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pseudo-instructions are needed on this family. Note, however, that
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because @code{@value{AS}} supports a simpler form of PC-relative
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addressing, you may simply write (for example)
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@example
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mov.l bar,r0
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@end example
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@noindent
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where other assemblers might require an explicit displacement to
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@code{bar} from the program counter:
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@example
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mov.l @@(@var{disp}, PC)
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@end example
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@ifset SMALL
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@c this table, due to the multi-col faking and hardcoded order, looks silly
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@c except in smallbook. See comments below "@set SMALL" near top of this file.
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Here is a summary of SH opcodes:
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@page
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@smallexample
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@i{Legend:}
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Rn @r{a numbered register}
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Rm @r{another numbered register}
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#imm @r{immediate data}
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disp @r{displacement}
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disp8 @r{8-bit displacement}
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disp12 @r{12-bit displacement}
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add #imm,Rn lds.l @@Rn+,PR
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add Rm,Rn mac.w @@Rm+,@@Rn+
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addc Rm,Rn mov #imm,Rn
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addv Rm,Rn mov Rm,Rn
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and #imm,R0 mov.b Rm,@@(R0,Rn)
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and Rm,Rn mov.b Rm,@@-Rn
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and.b #imm,@@(R0,GBR) mov.b Rm,@@Rn
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bf disp8 mov.b @@(disp,Rm),R0
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bra disp12 mov.b @@(disp,GBR),R0
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bsr disp12 mov.b @@(R0,Rm),Rn
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bt disp8 mov.b @@Rm+,Rn
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clrmac mov.b @@Rm,Rn
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clrt mov.b R0,@@(disp,Rm)
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cmp/eq #imm,R0 mov.b R0,@@(disp,GBR)
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cmp/eq Rm,Rn mov.l Rm,@@(disp,Rn)
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cmp/ge Rm,Rn mov.l Rm,@@(R0,Rn)
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cmp/gt Rm,Rn mov.l Rm,@@-Rn
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cmp/hi Rm,Rn mov.l Rm,@@Rn
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cmp/hs Rm,Rn mov.l @@(disp,Rn),Rm
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cmp/pl Rn mov.l @@(disp,GBR),R0
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cmp/pz Rn mov.l @@(disp,PC),Rn
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cmp/str Rm,Rn mov.l @@(R0,Rm),Rn
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div0s Rm,Rn mov.l @@Rm+,Rn
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div0u mov.l @@Rm,Rn
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div1 Rm,Rn mov.l R0,@@(disp,GBR)
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exts.b Rm,Rn mov.w Rm,@@(R0,Rn)
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exts.w Rm,Rn mov.w Rm,@@-Rn
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extu.b Rm,Rn mov.w Rm,@@Rn
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extu.w Rm,Rn mov.w @@(disp,Rm),R0
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jmp @@Rn mov.w @@(disp,GBR),R0
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jsr @@Rn mov.w @@(disp,PC),Rn
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ldc Rn,GBR mov.w @@(R0,Rm),Rn
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ldc Rn,SR mov.w @@Rm+,Rn
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ldc Rn,VBR mov.w @@Rm,Rn
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ldc.l @@Rn+,GBR mov.w R0,@@(disp,Rm)
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ldc.l @@Rn+,SR mov.w R0,@@(disp,GBR)
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ldc.l @@Rn+,VBR mova @@(disp,PC),R0
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lds Rn,MACH movt Rn
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lds Rn,MACL muls Rm,Rn
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lds Rn,PR mulu Rm,Rn
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lds.l @@Rn+,MACH neg Rm,Rn
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lds.l @@Rn+,MACL negc Rm,Rn
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@page
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nop stc VBR,Rn
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not Rm,Rn stc.l GBR,@@-Rn
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or #imm,R0 stc.l SR,@@-Rn
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or Rm,Rn stc.l VBR,@@-Rn
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or.b #imm,@@(R0,GBR) sts MACH,Rn
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rotcl Rn sts MACL,Rn
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rotcr Rn sts PR,Rn
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rotl Rn sts.l MACH,@@-Rn
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rotr Rn sts.l MACL,@@-Rn
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rte sts.l PR,@@-Rn
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rts sub Rm,Rn
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sett subc Rm,Rn
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shal Rn subv Rm,Rn
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shar Rn swap.b Rm,Rn
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shll Rn swap.w Rm,Rn
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shll16 Rn tas.b @@Rn
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shll2 Rn trapa #imm
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shll8 Rn tst #imm,R0
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shlr Rn tst Rm,Rn
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shlr16 Rn tst.b #imm,@@(R0,GBR)
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shlr2 Rn xor #imm,R0
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shlr8 Rn xor Rm,Rn
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sleep xor.b #imm,@@(R0,GBR)
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stc GBR,Rn xtrct Rm,Rn
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stc SR,Rn
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@end smallexample
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@end ifset
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@ifset Renesas-all
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@ifclear GENERIC
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@raisesections
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@end ifclear
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@end ifset
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