binutils-gdb/sim
Mike Frysinger c704d6e7ee sim: events: clean up trace casts
Don't blindly cast every possible type to (long).  Change to the right
printf format specifier whether it be a 64-bit type or a pointer.
2021-10-31 23:05:45 -04:00
..
aarch64 sim: rename ChangeLog files to ChangeLog-2021 2021-08-17 20:27:36 -04:00
arm sim: nltvals: localize TARGET_<open> defines 2021-10-31 04:50:44 -04:00
avr sim: rename ChangeLog files to ChangeLog-2021 2021-08-17 20:27:36 -04:00
bfin sim: filter out SIGSTKSZ [PR sim/28302] 2021-10-03 12:02:53 -04:00
bpf sim: tighten up stamp rules 2021-10-31 00:49:39 -04:00
common sim: events: clean up trace casts 2021-10-31 23:05:45 -04:00
cr16 sim: tighten up gencode output 2021-10-31 01:05:27 -04:00
cris sim: tighten up stamp rules 2021-10-31 00:49:39 -04:00
d10v sim: tighten up gencode output 2021-10-31 01:05:27 -04:00
erc32 sim: erc32: use silent build rules with sis linkage 2021-10-31 04:19:41 -04:00
example-synacor sim: rename ChangeLog files to ChangeLog-2021 2021-08-17 20:27:36 -04:00
frv sim: tighten up stamp rules 2021-10-31 00:49:39 -04:00
ft32 sim: rename ChangeLog files to ChangeLog-2021 2021-08-17 20:27:36 -04:00
h8300 sim: rename ChangeLog files to ChangeLog-2021 2021-08-17 20:27:36 -04:00
igen sim: igen: tighten up build output 2021-10-31 00:55:50 -04:00
iq2000 sim: tighten up stamp rules 2021-10-31 00:49:39 -04:00
lm32 sim: tighten up stamp rules 2021-10-31 00:49:39 -04:00
m4 sim: bfin: add support for SDL2 2021-09-13 22:45:19 -04:00
m32c sim: m32c: tighten up opc2c build output 2021-10-31 01:11:41 -04:00
m32r sim: drop unused targ-vals.h includes 2021-10-31 04:53:22 -04:00
m68hc11 sim: tighten up gencode output 2021-10-31 01:05:27 -04:00
mcore sim: rename ChangeLog files to ChangeLog-2021 2021-08-17 20:27:36 -04:00
microblaze sim: microblaze: replace custom basic types with common ones 2021-09-08 21:32:34 -04:00
mips sim: igen: tighten up build output 2021-10-31 00:55:50 -04:00
mn10300 sim: igen: tighten up build output 2021-10-31 00:55:50 -04:00
moxie sim: rename ChangeLog files to ChangeLog-2021 2021-08-17 20:27:36 -04:00
msp430 sim: drop unused targ-vals.h includes 2021-10-31 04:53:22 -04:00
or1k sim: tighten up stamp rules 2021-10-31 00:49:39 -04:00
ppc sim: ppc: handle \r in igen inputs [PR sim/28476] 2021-10-31 22:35:41 -04:00
pru sim: rename ChangeLog files to ChangeLog-2021 2021-08-17 20:27:36 -04:00
riscv sim: drop unused targ-vals.h includes 2021-10-31 04:53:22 -04:00
rl78 sim: rl78: drop obsolete manual dependency rules 2021-10-31 05:09:09 -04:00
rx sim: rename ChangeLog files to ChangeLog-2021 2021-08-17 20:27:36 -04:00
sh sim: tighten up gencode output 2021-10-31 01:05:27 -04:00
testsuite sim: rename ChangeLog files to ChangeLog-2021 2021-08-17 20:27:36 -04:00
v850 sim: v850: delete old gencode logic 2021-10-31 01:49:17 -04:00
.gitignore sim: rename ChangeLog files to ChangeLog-2021 2021-08-17 20:27:36 -04:00
aclocal.m4
arch-subdir.mk.in sim: ppc: fallback when ln is not available [PR sim/18864] 2021-10-03 11:36:30 -04:00
ChangeLog-2021 sim: rename ChangeLog files to ChangeLog-2021 2021-08-17 20:27:36 -04:00
config.h.in sim: bfin: add support for SDL2 2021-09-13 22:45:19 -04:00
configure sim: add arch-specific conditional logic 2021-10-31 02:03:16 -04:00
configure.ac sim: add arch-specific conditional logic 2021-10-31 02:03:16 -04:00
MAINTAINERS
Makefile.am sim: nltvals: switch output mode to a directory 2021-08-19 21:05:28 -04:00
Makefile.in sim: unify callback.o building 2021-10-31 04:51:44 -04:00
README-HACKING