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f2c29a1692
Rename .plt.bnd to .plt.sec to indicate that this is used as the second PLT section. There is no change in run-time behavior. We also scan the .plt.sec section to synthesize PLT symbols. bfd/ * elf64-x86-64.c (elf_x86_64_link_hash_entry): Rename plt_bnd to plt_second. (elf_x86_64_link_hash_table): Rename plt_bnd/plt_bnd_eh_frame to plt_second/plt_second_eh_frame. (elf_x86_64_link_hash_newfunc): Updated. (elf_x86_64_allocate_dynrelocs): Likewise. (elf_x86_64_size_dynamic_sections): Likewise. (elf_x86_64_relocate_section): Likewise. (elf_x86_64_finish_dynamic_symbol): Likewise. (elf_x86_64_finish_dynamic_sections): Likewise. (elf_x86_64_plt_type): Rename plt_bnd to plt_second. (elf_x86_64_get_synthetic_symtab): Updated. Also scan the .plt.sec section. (elf_backend_setup_gnu_properties): Updated. Create the .plt.sec section instead of the .plt.sec section. ld/ * emulparams/elf_x86_64.sh (TINY_READONLY_SECTION): Replace .plt.bnd with .plt.sec. * testsuite/ld-x86-64/bnd-ifunc-1-now.d: Likewise. * testsuite/ld-x86-64/bnd-ifunc-2-now.d: Likewise. * testsuite/ld-x86-64/bnd-ifunc-2.d: Likewise. * testsuite/ld-x86-64/bnd-plt-1-now.d: Likewise. * testsuite/ld-x86-64/bnd-plt-1.d: Likewise. * testsuite/ld-x86-64/mpx3.dd: Likewise. * testsuite/ld-x86-64/mpx3n.dd: Likewise. * testsuite/ld-x86-64/mpx4.dd: Likewise. * testsuite/ld-x86-64/mpx4n.dd: Likewise. * testsuite/ld-x86-64/plt-main-bnd-now.rd: Likewise. * testsuite/ld-x86-64/pr21038b-now.d: Likewise. * testsuite/ld-x86-64/pr21038b.d: Likewise. * testsuite/ld-x86-64/pr21038c-now.d: Likewise. * testsuite/ld-x86-64/pr21038c.d: Likewise.
70 lines
2.0 KiB
Makefile
70 lines
2.0 KiB
Makefile
#name: PR ld/21038 (.plt.sec)
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#as: --64
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#ld: -z bndplt -melf_x86_64 -shared -z relro --ld-generated-unwind-info
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#objdump: -dw -Wf
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.*: +file format .*
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Contents of the .eh_frame section:
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0+ 0000000000000014 00000000 CIE
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Version: 1
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Augmentation: "zR"
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Code alignment factor: 1
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Data alignment factor: -8
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Return address column: 16
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Augmentation data: 1b
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DW_CFA_def_cfa: r7 \(rsp\) ofs 8
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DW_CFA_offset: r16 \(rip\) at cfa-8
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DW_CFA_nop
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DW_CFA_nop
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0+18 0000000000000014 0000001c FDE cie=00000000 pc=0000000000000248..000000000000024d
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DW_CFA_nop
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DW_CFA_nop
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DW_CFA_nop
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DW_CFA_nop
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DW_CFA_nop
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DW_CFA_nop
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DW_CFA_nop
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0+30 0000000000000024 00000034 FDE cie=00000000 pc=0000000000000220..0000000000000240
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DW_CFA_def_cfa_offset: 16
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DW_CFA_advance_loc: 6 to 0000000000000226
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DW_CFA_def_cfa_offset: 24
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DW_CFA_advance_loc: 10 to 0000000000000230
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DW_CFA_def_cfa_expression \(DW_OP_breg7 \(rsp\): 8; DW_OP_breg16 \(rip\): 0; DW_OP_lit15; DW_OP_and; DW_OP_lit5; DW_OP_ge; DW_OP_lit3; DW_OP_shl; DW_OP_plus\)
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DW_CFA_nop
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DW_CFA_nop
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DW_CFA_nop
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DW_CFA_nop
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0+58 0000000000000010 0000005c FDE cie=00000000 pc=0000000000000240..0000000000000248
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DW_CFA_nop
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DW_CFA_nop
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DW_CFA_nop
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Disassembly of section .plt:
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0+220 <.plt>:
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+[a-f0-9]+: ff 35 e2 0d 20 00 pushq 0x200de2\(%rip\) # 201008 <_GLOBAL_OFFSET_TABLE_\+0x8>
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+[a-f0-9]+: f2 ff 25 e3 0d 20 00 bnd jmpq \*0x200de3\(%rip\) # 201010 <_GLOBAL_OFFSET_TABLE_\+0x10>
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+[a-f0-9]+: 0f 1f 00 nopl \(%rax\)
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+[a-f0-9]+: 68 00 00 00 00 pushq \$0x0
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+[a-f0-9]+: f2 e9 e5 ff ff ff bnd jmpq 220 <.plt>
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+[a-f0-9]+: 0f 1f 44 00 00 nopl 0x0\(%rax,%rax,1\)
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Disassembly of section .plt.sec:
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0+240 <func@plt>:
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+[a-f0-9]+: f2 ff 25 d1 0d 20 00 bnd jmpq \*0x200dd1\(%rip\) # 201018 <func>
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+[a-f0-9]+: 90 nop
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Disassembly of section .text:
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0+248 <foo>:
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+[a-f0-9]+: e8 f3 ff ff ff callq 240 <func@plt>
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#pass
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