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https://sourceware.org/git/binutils-gdb.git
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d1023b5d1e
Don't ignore buffer memory read failure, or malloc failure. Lots of functions get a return status to pass these failures up the chain in this patch. opcodes/ * s12z-dis.c (abstract_read_memory): Don't print error on EOI. * s12z-opc.c: Formatting. (operands_f): Return an int. (opr_n_bytes_p1): Return -1 on reaching buffer memory limit. (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes), (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes), (exg_sex_discrim): Likewise. (create_immediate_operand, create_bitfield_operand), (create_register_operand_with_size, create_register_all_operand), (create_register_all16_operand, create_simple_memory_operand), (create_memory_operand, create_memory_auto_operand): Don't segfault on malloc failure. (z_ext24_decode): Return an int status, negative on fail, zero on success. (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2), (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base), (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7), (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x), (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode), (mov_imm_opr, ld_18bit_decode, exg_sex_decode), (loop_primitive_decode, shift_decode, psh_pul_decode), (bit_field_decode): Similarly. (z_decode_signed_value, decode_signed_value): Similarly. Add arg to return value, update callers. (x_opr_decode_with_size): Check all reads, returning NULL on fail. Don't segfault on NULL operand. (decode_operation): Return OP_INVALID on first fail. (decode_s12z): Check all reads, returning -1 on fail. gas/ * testsuite/gas/s12z/truncated.d: Update expected output.
408 lines
8.7 KiB
C
408 lines
8.7 KiB
C
/* s12z-dis.c -- Freescale S12Z disassembly
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Copyright (C) 2018-2020 Free Software Foundation, Inc.
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This file is part of the GNU opcodes library.
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This library is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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It is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
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MA 02110-1301, USA. */
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#include "sysdep.h"
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#include <stdio.h>
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#include "bfd_stdint.h"
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#include <stdbool.h>
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#include <assert.h>
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#include "opcode/s12z.h"
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#include "bfd.h"
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#include "dis-asm.h"
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#include "disassemble.h"
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#include "s12z-opc.h"
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#include "opintl.h"
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struct mem_read_abstraction
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{
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struct mem_read_abstraction_base base;
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bfd_vma memaddr;
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struct disassemble_info* info;
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};
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static void
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advance (struct mem_read_abstraction_base *b)
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{
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struct mem_read_abstraction *mra = (struct mem_read_abstraction *) b;
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mra->memaddr ++;
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}
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static bfd_vma
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posn (struct mem_read_abstraction_base *b)
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{
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struct mem_read_abstraction *mra = (struct mem_read_abstraction *) b;
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return mra->memaddr;
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}
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static int
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abstract_read_memory (struct mem_read_abstraction_base *b,
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int offset,
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size_t n, bfd_byte *bytes)
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{
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struct mem_read_abstraction *mra = (struct mem_read_abstraction *) b;
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int status = (*mra->info->read_memory_func) (mra->memaddr + offset,
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bytes, n, mra->info);
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return status != 0 ? -1 : 0;
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}
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/* Start of disassembly file. */
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const struct reg registers[S12Z_N_REGISTERS] =
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{
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{"d2", 2},
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{"d3", 2},
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{"d4", 2},
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{"d5", 2},
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{"d0", 1},
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{"d1", 1},
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{"d6", 4},
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{"d7", 4},
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{"x", 3},
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{"y", 3},
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{"s", 3},
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{"p", 3},
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{"cch", 1},
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{"ccl", 1},
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{"ccw", 2}
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};
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static const char *mnemonics[] =
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{
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"!!invalid!!",
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"psh",
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"pul",
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"tbne", "tbeq", "tbpl", "tbmi", "tbgt", "tble",
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"dbne", "dbeq", "dbpl", "dbmi", "dbgt", "dble",
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"sex",
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"exg",
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"lsl", "lsr",
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"asl", "asr",
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"rol", "ror",
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"bfins", "bfext",
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"trap",
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"ld",
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"st",
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"cmp",
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"stop",
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"wai",
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"sys",
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"minu",
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"mins",
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"maxu",
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"maxs",
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"abs",
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"adc",
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"bit",
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"sbc",
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"rti",
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"clb",
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"eor",
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"sat",
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"nop",
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"bgnd",
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"brclr",
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"brset",
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"rts",
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"lea",
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"mov",
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"bra",
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"bsr",
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"bhi",
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"bls",
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"bcc",
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"bcs",
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"bne",
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"beq",
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"bvc",
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"bvs",
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"bpl",
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"bmi",
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"bge",
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"blt",
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"bgt",
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"ble",
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"inc",
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"clr",
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"dec",
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"add",
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"sub",
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"and",
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"or",
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"tfr",
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"jmp",
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"jsr",
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"com",
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"andcc",
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"neg",
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"orcc",
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"bclr",
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"bset",
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"btgl",
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"swi",
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"mulu",
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"divu",
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"modu",
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"macu",
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"qmulu",
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"muls",
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"divs",
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"mods",
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"macs",
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"qmuls",
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NULL
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};
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static void
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operand_separator (struct disassemble_info *info)
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{
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if ((info->flags & 0x2))
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(*info->fprintf_func) (info->stream, ",");
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(*info->fprintf_func) (info->stream, " ");
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info->flags |= 0x2;
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}
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/* Render the symbol name whose value is ADDR + BASE or the adddress itself if
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there is no symbol. If BASE is non zero, then the a PC relative adddress is
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assumend (ie BASE is the value in the PC. */
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static void
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decode_possible_symbol (bfd_vma addr, bfd_vma base,
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struct disassemble_info *info, bool relative)
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{
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const char *fmt = relative ? "*%+" BFD_VMA_FMT "d" : "%" BFD_VMA_FMT "d";
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if (!info->symbol_at_address_func (addr + base, info))
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{
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(*info->fprintf_func) (info->stream, fmt, addr);
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}
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else
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{
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asymbol *sym = NULL;
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int j;
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for (j = 0; j < info->symtab_size; ++j)
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{
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sym = info->symtab[j];
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if (bfd_asymbol_value (sym) == addr + base)
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{
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break;
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}
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}
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if (j < info->symtab_size)
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(*info->fprintf_func) (info->stream, "%s", bfd_asymbol_name (sym));
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else
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(*info->fprintf_func) (info->stream, fmt, addr);
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}
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}
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/* Emit the disassembled text for OPR */
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static void
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opr_emit_disassembly (const struct operand *opr,
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struct disassemble_info *info)
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{
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operand_separator (info);
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switch (opr->cl)
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{
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case OPND_CL_IMMEDIATE:
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(*info->fprintf_func) (info->stream, "#%d",
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((struct immediate_operand *) opr)->value);
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break;
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case OPND_CL_REGISTER:
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{
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int r = ((struct register_operand*) opr)->reg;
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if (r < 0 || r >= S12Z_N_REGISTERS)
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(*info->fprintf_func) (info->stream, _("<illegal reg num>"));
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else
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(*info->fprintf_func) (info->stream, "%s", registers[r].name);
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}
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break;
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case OPND_CL_REGISTER_ALL16:
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(*info->fprintf_func) (info->stream, "%s", "ALL16b");
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break;
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case OPND_CL_REGISTER_ALL:
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(*info->fprintf_func) (info->stream, "%s", "ALL");
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break;
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case OPND_CL_BIT_FIELD:
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(*info->fprintf_func) (info->stream, "#%d:%d",
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((struct bitfield_operand*)opr)->width,
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((struct bitfield_operand*)opr)->offset);
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break;
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case OPND_CL_SIMPLE_MEMORY:
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{
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struct simple_memory_operand *mo =
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(struct simple_memory_operand *) opr;
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decode_possible_symbol (mo->addr, mo->base, info, mo->relative);
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}
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break;
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case OPND_CL_MEMORY:
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{
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int used_reg = 0;
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struct memory_operand *mo = (struct memory_operand *) opr;
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(*info->fprintf_func) (info->stream, "%c", mo->indirect ? '[' : '(');
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const char *fmt;
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assert (mo->mutation == OPND_RM_NONE || mo->n_regs == 1);
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switch (mo->mutation)
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{
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case OPND_RM_PRE_DEC:
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fmt = "-%s";
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break;
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case OPND_RM_PRE_INC:
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fmt = "+%s";
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break;
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case OPND_RM_POST_DEC:
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fmt = "%s-";
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break;
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case OPND_RM_POST_INC:
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fmt = "%s+";
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break;
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case OPND_RM_NONE:
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default:
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if (mo->n_regs < 2)
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(*info->fprintf_func) (info->stream, (mo->n_regs == 0) ? "%d" : "%d,", mo->base_offset);
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fmt = "%s";
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break;
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}
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if (mo->n_regs > 0)
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{
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int r = mo->regs[0];
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if (r < 0 || r >= S12Z_N_REGISTERS)
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(*info->fprintf_func) (info->stream, fmt, _("<illegal reg num>"));
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else
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(*info->fprintf_func) (info->stream, fmt, registers[r].name);
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}
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used_reg = 1;
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if (mo->n_regs > used_reg)
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{
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int r = mo->regs[used_reg];
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if (r < 0 || r >= S12Z_N_REGISTERS)
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(*info->fprintf_func) (info->stream, _("<illegal reg num>"));
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else
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(*info->fprintf_func) (info->stream, ",%s",
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registers[r].name);
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}
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(*info->fprintf_func) (info->stream, "%c",
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mo->indirect ? ']' : ')');
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}
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break;
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};
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}
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#define S12Z_N_SIZES 4
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static const char shift_size_table[S12Z_N_SIZES] =
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{
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'b', 'w', 'p', 'l'
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};
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int
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print_insn_s12z (bfd_vma memaddr, struct disassemble_info* info)
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{
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int o;
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enum optr operator = OP_INVALID;
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int n_operands = 0;
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/* The longest instruction in S12Z can have 6 operands.
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(Most have 3 or less. Only PSH and PUL have so many. */
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struct operand *operands[6];
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struct mem_read_abstraction mra;
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mra.base.read = (void *) abstract_read_memory ;
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mra.base.advance = advance ;
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mra.base.posn = posn;
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mra.memaddr = memaddr;
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mra.info = info;
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short osize = -1;
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int n_bytes =
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decode_s12z (&operator, &osize, &n_operands, operands,
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(struct mem_read_abstraction_base *) &mra);
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(info->fprintf_func) (info->stream, "%s", mnemonics[(long)operator]);
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/* Ship out size sufficies for those instructions which
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need them. */
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if (osize == -1)
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{
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bool suffix = false;
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for (o = 0; o < n_operands; ++o)
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{
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if (operands[o] && operands[o]->osize != -1)
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{
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if (!suffix)
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{
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(*mra.info->fprintf_func) (mra.info->stream, "%c", '.');
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suffix = true;
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}
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osize = operands[o]->osize;
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if (osize < 0 || osize >= S12Z_N_SIZES)
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(*mra.info->fprintf_func) (mra.info->stream, _("<bad>"));
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else
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(*mra.info->fprintf_func) (mra.info->stream, "%c",
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shift_size_table[osize]);
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}
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}
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}
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else
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{
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if (osize < 0 || osize >= S12Z_N_SIZES)
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(*mra.info->fprintf_func) (mra.info->stream, _(".<bad>"));
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else
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(*mra.info->fprintf_func) (mra.info->stream, ".%c",
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shift_size_table[osize]);
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}
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/* Ship out the operands. */
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for (o = 0; o < n_operands; ++o)
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{
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if (operands[o])
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opr_emit_disassembly (operands[o], mra.info);
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free (operands[o]);
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}
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return n_bytes;
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}
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