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7179e0e6b2
include/ 2017-07-19 Claudiu Zissulescu <claziss@synopsys.com> * opcode/arc.h (SJLI): Add. opcode/ 2017-07-19 Claudiu Zissulescu <claziss@synopsys.com> * arc-opc.c (extract_uimm12_20): New function. (UIMM12_20): New operand. (SIMM3_5_S): Adjust. * arc-tbl.h (sjli): Add new instruction.
671 lines
22 KiB
C
671 lines
22 KiB
C
/* Opcode table for the ARC.
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Copyright (C) 1994-2017 Free Software Foundation, Inc.
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Contributed by Claudiu Zissulescu (claziss@synopsys.com)
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This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and
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the GNU Binutils.
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GAS/GDB is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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GAS/GDB is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with GAS or GDB; see the file COPYING3. If not, write to
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the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
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MA 02110-1301, USA. */
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#ifndef OPCODE_ARC_H
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#define OPCODE_ARC_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifndef MAX_INSN_ARGS
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#define MAX_INSN_ARGS 16
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#endif
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#ifndef MAX_INSN_FLGS
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#define MAX_INSN_FLGS 4
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#endif
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/* Instruction Class. */
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typedef enum
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{
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ACL,
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ARITH,
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AUXREG,
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BBIT0,
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BBIT1,
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BI,
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BIH,
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BITOP,
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BITSTREAM,
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BMU,
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BRANCH,
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BRCC,
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CONTROL,
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DIVREM,
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DMA,
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DPI,
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DSP,
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EI,
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ENTER,
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FLOAT,
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INVALID,
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JLI,
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JUMP,
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KERNEL,
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LEAVE,
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LOAD,
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LOGICAL,
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LOOP,
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MEMORY,
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MISC,
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MOVE,
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MPY,
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NET,
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PROTOCOL_DECODE,
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PMU,
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POP,
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PUSH,
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SJLI,
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STORE,
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SUB,
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ULTRAIP,
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XY
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} insn_class_t;
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/* Instruction Subclass. */
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typedef enum
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{
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NONE = 0,
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CVT = (1U << 1),
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BTSCN = (1U << 2),
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CD = (1U << 3),
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CD1 = CD,
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CD2 = CD,
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COND = (1U << 4),
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DIV = (1U << 5),
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DP = (1U << 6),
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DPA = (1U << 7),
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DPX = (1U << 8),
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LL64 = (1U << 9),
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MPY1E = (1U << 10),
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MPY6E = (1U << 11),
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MPY7E = (1U << 12),
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MPY8E = (1U << 13),
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MPY9E = (1U << 14),
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NPS400 = (1U << 15),
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QUARKSE1 = (1U << 16),
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QUARKSE2 = (1U << 17),
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SHFT1 = (1U << 18),
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SHFT2 = (1U << 19),
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SWAP = (1U << 20),
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SP = (1U << 21),
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SPX = (1U << 22)
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} insn_subclass_t;
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/* Flags class. */
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typedef enum
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{
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F_CLASS_NONE = 0,
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/* At most one flag from the set of flags can appear in the
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instruction. */
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F_CLASS_OPTIONAL = (1 << 0),
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/* Exactly one from from the set of flags must appear in the
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instruction. */
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F_CLASS_REQUIRED = (1 << 1),
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/* The conditional code can be extended over the standard variants
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via .extCondCode pseudo-op. */
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F_CLASS_EXTEND = (1 << 2),
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/* Condition code flag. */
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F_CLASS_COND = (1 << 3),
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/* Write back mode. */
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F_CLASS_WB = (1 << 4),
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/* Data size. */
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F_CLASS_ZZ = (1 << 5),
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/* Implicit flag. */
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F_CLASS_IMPLICIT = (1 << 6)
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} flag_class_t;
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/* The opcode table is an array of struct arc_opcode. */
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struct arc_opcode
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{
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/* The opcode name. */
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const char * name;
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/* The opcode itself. Those bits which will be filled in with
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operands are zeroes. */
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unsigned long long opcode;
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/* The opcode mask. This is used by the disassembler. This is a
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mask containing ones indicating those bits which must match the
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opcode field, and zeroes indicating those bits which need not
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match (and are presumably filled in by operands). */
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unsigned long long mask;
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/* One bit flags for the opcode. These are primarily used to
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indicate specific processors and environments support the
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instructions. The defined values are listed below. */
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unsigned cpu;
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/* The instruction class. This is used by gdb. */
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insn_class_t insn_class;
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/* The instruction subclass. */
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insn_subclass_t subclass;
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/* An array of operand codes. Each code is an index into the
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operand table. They appear in the order which the operands must
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appear in assembly code, and are terminated by a zero. */
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unsigned char operands[MAX_INSN_ARGS + 1];
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/* An array of flag codes. Each code is an index into the flag
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table. They appear in the order which the flags must appear in
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assembly code, and are terminated by a zero. */
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unsigned char flags[MAX_INSN_FLGS + 1];
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};
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/* The table itself is sorted by major opcode number, and is otherwise
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in the order in which the disassembler should consider
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instructions. */
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extern const struct arc_opcode arc_opcodes[];
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/* Return length of an instruction represented by OPCODE, in bytes. */
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extern int arc_opcode_len (const struct arc_opcode *opcode);
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/* CPU Availability. */
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#define ARC_OPCODE_NONE 0x0000
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#define ARC_OPCODE_ARC600 0x0001 /* ARC 600 specific insns. */
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#define ARC_OPCODE_ARC700 0x0002 /* ARC 700 specific insns. */
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#define ARC_OPCODE_ARCv2EM 0x0004 /* ARCv2 EM specific insns. */
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#define ARC_OPCODE_ARCv2HS 0x0008 /* ARCv2 HS specific insns. */
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/* CPU combi. */
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#define ARC_OPCODE_ARCALL (ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 \
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| ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS)
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#define ARC_OPCODE_ARCFPX (ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM)
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#define ARC_OPCODE_ARCV2 (ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS)
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#define ARC_OPCODE_ARCMPY6E (ARC_OPCODE_ARC700 | ARC_OPCODE_ARCV2)
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/* The operands table is an array of struct arc_operand. */
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struct arc_operand
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{
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/* The number of bits in the operand. */
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unsigned int bits;
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/* How far the operand is left shifted in the instruction. */
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unsigned int shift;
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/* The default relocation type for this operand. */
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signed int default_reloc;
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/* One bit syntax flags. */
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unsigned int flags;
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/* Insertion function. This is used by the assembler. To insert an
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operand value into an instruction, check this field.
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If it is NULL, execute
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i |= (op & ((1 << o->bits) - 1)) << o->shift;
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(i is the instruction which we are filling in, o is a pointer to
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this structure, and op is the opcode value; this assumes twos
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complement arithmetic).
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If this field is not NULL, then simply call it with the
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instruction and the operand value. It will return the new value
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of the instruction. If the ERRMSG argument is not NULL, then if
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the operand value is illegal, *ERRMSG will be set to a warning
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string (the operand will be inserted in any case). If the
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operand value is legal, *ERRMSG will be unchanged (most operands
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can accept any value). */
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unsigned long long (*insert) (unsigned long long instruction,
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long long int op,
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const char **errmsg);
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/* Extraction function. This is used by the disassembler. To
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extract this operand type from an instruction, check this field.
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If it is NULL, compute
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op = ((i) >> o->shift) & ((1 << o->bits) - 1);
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if ((o->flags & ARC_OPERAND_SIGNED) != 0
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&& (op & (1 << (o->bits - 1))) != 0)
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op -= 1 << o->bits;
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(i is the instruction, o is a pointer to this structure, and op
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is the result; this assumes twos complement arithmetic).
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If this field is not NULL, then simply call it with the
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instruction value. It will return the value of the operand. If
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the INVALID argument is not NULL, *INVALID will be set to
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TRUE if this operand type can not actually be extracted from
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this operand (i.e., the instruction does not match). If the
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operand is valid, *INVALID will not be changed. */
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long long int (*extract) (unsigned long long instruction,
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bfd_boolean *invalid);
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};
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/* Elements in the table are retrieved by indexing with values from
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the operands field of the arc_opcodes table. */
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extern const struct arc_operand arc_operands[];
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extern const unsigned arc_num_operands;
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extern const unsigned arc_Toperand;
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extern const unsigned arc_NToperand;
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/* Values defined for the flags field of a struct arc_operand. */
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/* This operand does not actually exist in the assembler input. This
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is used to support extended mnemonics, for which two operands fields
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are identical. The assembler should call the insert function with
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any op value. The disassembler should call the extract function,
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ignore the return value, and check the value placed in the invalid
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argument. */
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#define ARC_OPERAND_FAKE 0x0001
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/* This operand names an integer register. */
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#define ARC_OPERAND_IR 0x0002
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/* This operand takes signed values. */
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#define ARC_OPERAND_SIGNED 0x0004
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/* This operand takes unsigned values. This exists primarily so that
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a flags value of 0 can be treated as end-of-arguments. */
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#define ARC_OPERAND_UNSIGNED 0x0008
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/* This operand takes long immediate values. */
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#define ARC_OPERAND_LIMM 0x0010
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/* This operand is identical like the previous one. */
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#define ARC_OPERAND_DUPLICATE 0x0020
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/* This operand is PC relative. Used for internal relocs. */
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#define ARC_OPERAND_PCREL 0x0040
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/* This operand is truncated. The truncation is done accordingly to
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operand alignment attribute. */
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#define ARC_OPERAND_TRUNCATE 0x0080
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/* This operand is 16bit aligned. */
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#define ARC_OPERAND_ALIGNED16 0x0100
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/* This operand is 32bit aligned. */
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#define ARC_OPERAND_ALIGNED32 0x0200
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/* This operand can be ignored by matching process if it is not
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present. */
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#define ARC_OPERAND_IGNORE 0x0400
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/* Don't check the range when matching. */
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#define ARC_OPERAND_NCHK 0x0800
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/* Mark the braket possition. */
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#define ARC_OPERAND_BRAKET 0x1000
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/* Address type operand for NPS400. */
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#define ARC_OPERAND_ADDRTYPE 0x2000
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/* Mark the colon position. */
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#define ARC_OPERAND_COLON 0x4000
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/* Mask for selecting the type for typecheck purposes. */
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#define ARC_OPERAND_TYPECHECK_MASK \
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(ARC_OPERAND_IR \
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| ARC_OPERAND_LIMM | ARC_OPERAND_SIGNED \
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| ARC_OPERAND_UNSIGNED | ARC_OPERAND_BRAKET \
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| ARC_OPERAND_ADDRTYPE | ARC_OPERAND_COLON)
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/* Macro to determine if an operand is a fake operand. */
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#define ARC_OPERAND_IS_FAKE(op) \
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((operand->flags & ARC_OPERAND_FAKE) \
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&& !((operand->flags & ARC_OPERAND_BRAKET) \
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|| (operand->flags & ARC_OPERAND_COLON)))
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/* The flags structure. */
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struct arc_flag_operand
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{
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/* The flag name. */
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const char * name;
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/* The flag code. */
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unsigned code;
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/* The number of bits in the operand. */
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unsigned int bits;
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/* How far the operand is left shifted in the instruction. */
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unsigned int shift;
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/* Available for disassembler. */
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unsigned char favail;
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};
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/* The flag operands table. */
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extern const struct arc_flag_operand arc_flag_operands[];
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extern const unsigned arc_num_flag_operands;
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/* The flag's class structure. */
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struct arc_flag_class
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{
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/* Flag class. */
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flag_class_t flag_class;
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/* List of valid flags (codes). */
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unsigned flags[256];
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};
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extern const struct arc_flag_class arc_flag_classes[];
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/* Structure for special cases. */
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struct arc_flag_special
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{
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/* Name of special case instruction. */
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const char *name;
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/* List of flags applicable for special case instruction. */
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unsigned flags[32];
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};
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extern const struct arc_flag_special arc_flag_special_cases[];
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extern const unsigned arc_num_flag_special;
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/* Relocation equivalence structure. */
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struct arc_reloc_equiv_tab
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{
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const char * name; /* String to lookup. */
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const char * mnemonic; /* Extra matching condition. */
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unsigned flags[32]; /* Extra matching condition. */
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signed int oldreloc; /* Old relocation. */
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signed int newreloc; /* New relocation. */
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};
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extern const struct arc_reloc_equiv_tab arc_reloc_equiv[];
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extern const unsigned arc_num_equiv_tab;
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/* Structure for operand operations for pseudo/alias instructions. */
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struct arc_operand_operation
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{
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/* The index for operand from operand array. */
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unsigned operand_idx;
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/* Defines if it needs the operand inserted by the assembler or
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whether this operand comes from the pseudo instruction's
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operands. */
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unsigned char needs_insert;
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/* Count we have to add to the operand. Use negative number to
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subtract from the operand. Also use this number to add to 0 if
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the operand needs to be inserted (i.e. needs_insert == 1). */
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int count;
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/* Index of the operand to swap with. To be done AFTER applying
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inc_count. */
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unsigned swap_operand_idx;
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};
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/* Structure for pseudo/alias instructions. */
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struct arc_pseudo_insn
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{
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/* Mnemonic for pseudo/alias insn. */
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const char * mnemonic_p;
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/* Mnemonic for real instruction. */
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const char * mnemonic_r;
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/* Flag that will have to be added (if any). */
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const char * flag_r;
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/* Amount of operands. */
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unsigned operand_cnt;
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/* Array of operand operations. */
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struct arc_operand_operation operand[6];
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};
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extern const struct arc_pseudo_insn arc_pseudo_insns[];
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extern const unsigned arc_num_pseudo_insn;
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/* Structure for AUXILIARY registers. */
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struct arc_aux_reg
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{
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/* Register address. */
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int address;
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/* One bit flags for the opcode. These are primarily used to
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indicate specific processors and environments support the
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instructions. */
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unsigned cpu;
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/* AUX register subclass. */
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insn_subclass_t subclass;
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/* Register name. */
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const char * name;
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/* Size of the string. */
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size_t length;
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};
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extern const struct arc_aux_reg arc_aux_regs[];
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extern const unsigned arc_num_aux_regs;
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extern const struct arc_opcode arc_relax_opcodes[];
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extern const unsigned arc_num_relax_opcodes;
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/* Macro used for generating one class of NPS instructions. */
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#define NPS_CMEM_HIGH_VALUE 0x57f0
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/* Macros to help generating regular pattern instructions. */
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#define FIELDA(word) (word & 0x3F)
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#define FIELDB(word) (((word & 0x07) << 24) | (((word >> 3) & 0x07) << 12))
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#define FIELDC(word) ((word & 0x3F) << 6)
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#define FIELDF (0x01 << 15)
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#define FIELDQ (0x1F)
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#define INSN3OP(MOP,SOP) (((MOP & 0x1F) << 27) | ((SOP & 0x3F) << 16))
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#define INSN2OPX(MOP,SOP1,SOP2) (INSN3OP (MOP,SOP1) | (SOP2 & 0x3F))
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#define INSN2OP(MOP,SOP) (INSN2OPX (MOP,0x2F,SOP))
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#define INSN3OP_ABC(MOP,SOP) (INSN3OP (MOP,SOP))
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#define INSN3OP_ALC(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDB (62))
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#define INSN3OP_ABL(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDC (62))
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#define INSN3OP_ALL(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDB (62) | FIELDC (62))
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#define INSN3OP_0BC(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDA (62))
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#define INSN3OP_0LC(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDA (62) | FIELDB (62))
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#define INSN3OP_0BL(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDA (62) | FIELDC (62))
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#define INSN3OP_0LL(MOP,SOP) \
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(INSN3OP (MOP,SOP) | FIELDA (62) | FIELDB (62) | FIELDC (62))
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#define INSN3OP_ABU(MOP,SOP) (INSN3OP (MOP,SOP) | (0x01 << 22))
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#define INSN3OP_ALU(MOP,SOP) (INSN3OP (MOP,SOP) | (0x01 << 22) | FIELDB (62))
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#define INSN3OP_0BU(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDA (62) | (0x01 << 22))
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#define INSN3OP_0LU(MOP,SOP) \
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(INSN3OP (MOP,SOP) | FIELDA (62) | (0x01 << 22) | FIELDB (62))
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#define INSN3OP_BBS(MOP,SOP) (INSN3OP (MOP,SOP) | (0x02 << 22))
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#define INSN3OP_0LS(MOP,SOP) (INSN3OP (MOP,SOP) | (0x02 << 22) | FIELDB (62))
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#define INSN3OP_CBBC(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22))
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#define INSN3OP_CBBL(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22) | FIELDC (62))
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#define INSN3OP_C0LC(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22) | FIELDB (62))
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#define INSN3OP_C0LL(MOP,SOP) \
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(INSN3OP (MOP,SOP) | (0x03 << 22) | FIELDC (62) | FIELDB (62))
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#define INSN3OP_CBBU(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22) | (0x01 << 5))
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#define INSN3OP_C0LU(MOP,SOP) \
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(INSN3OP (MOP,SOP) | (0x03 << 22) | (0x01 << 5) | FIELDB (62))
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#define MASK_32BIT(VAL) (0xffffffff & (VAL))
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#define MINSN3OP_ABC (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDB (63) | FIELDC (63))))
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#define MINSN3OP_ALC (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDC (63))))
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#define MINSN3OP_ABL (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDB (63))))
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#define MINSN3OP_ALL (MASK_32BIT (~(FIELDF | FIELDA (63))))
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#define MINSN3OP_0BC (MASK_32BIT (~(FIELDF | FIELDB (63) | FIELDC (63))))
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#define MINSN3OP_0LC (MASK_32BIT (~(FIELDF | FIELDC (63))))
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#define MINSN3OP_0BL (MASK_32BIT (~(FIELDF | FIELDB (63))))
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#define MINSN3OP_0LL (MASK_32BIT (~(FIELDF)))
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#define MINSN3OP_ABU (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDB (63) | FIELDC (63))))
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#define MINSN3OP_ALU (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDC (63))))
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#define MINSN3OP_0BU (MASK_32BIT (~(FIELDF | FIELDB (63) | FIELDC (63))))
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#define MINSN3OP_0LU (MASK_32BIT (~(FIELDF | FIELDC (63))))
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#define MINSN3OP_BBS (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDB (63) | FIELDC (63))))
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#define MINSN3OP_0LS (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDC (63))))
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#define MINSN3OP_CBBC (MASK_32BIT (~(FIELDF | FIELDQ | FIELDB (63) | FIELDC (63))))
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#define MINSN3OP_CBBL (MASK_32BIT (~(FIELDF | FIELDQ | FIELDB (63))))
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#define MINSN3OP_C0LC (MASK_32BIT (~(FIELDF | FIELDQ | FIELDC (63))))
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#define MINSN3OP_C0LL (MASK_32BIT (~(FIELDF | FIELDQ)))
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#define MINSN3OP_CBBU (MASK_32BIT (~(FIELDF | FIELDQ | FIELDB (63) | FIELDC (63))))
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#define MINSN3OP_C0LU (MASK_32BIT (~(FIELDF | FIELDQ | FIELDC (63))))
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#define INSN2OP_BC(MOP,SOP) (INSN2OP (MOP,SOP))
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#define INSN2OP_BL(MOP,SOP) (INSN2OP (MOP,SOP) | FIELDC (62))
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#define INSN2OP_0C(MOP,SOP) (INSN2OP (MOP,SOP) | FIELDB (62))
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#define INSN2OP_0L(MOP,SOP) (INSN2OP (MOP,SOP) | FIELDB (62) | FIELDC (62))
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#define INSN2OP_BU(MOP,SOP) (INSN2OP (MOP,SOP) | (0x01 << 22))
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#define INSN2OP_0U(MOP,SOP) (INSN2OP (MOP,SOP) | (0x01 << 22) | FIELDB (62))
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#define MINSN2OP_BC (MASK_32BIT ((~(FIELDF | FIELDB (63) | FIELDC (63)))))
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#define MINSN2OP_BL (MASK_32BIT ((~(FIELDF | FIELDB (63)))))
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#define MINSN2OP_0C (MASK_32BIT ((~(FIELDF | FIELDC (63)))))
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#define MINSN2OP_0L (MASK_32BIT ((~(FIELDF))))
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#define MINSN2OP_BU (MASK_32BIT ((~(FIELDF | FIELDB (63) | FIELDC (63)))))
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#define MINSN2OP_0U (MASK_32BIT ((~(FIELDF | FIELDC (63)))))
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/* Various constants used when defining an extension instruction. */
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#define ARC_SYNTAX_3OP (1 << 0)
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#define ARC_SYNTAX_2OP (1 << 1)
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#define ARC_SYNTAX_1OP (1 << 2)
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#define ARC_SYNTAX_NOP (1 << 3)
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#define ARC_SYNTAX_MASK (0x0F)
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#define ARC_OP1_MUST_BE_IMM (1 << 0)
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#define ARC_OP1_IMM_IMPLIED (1 << 1)
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#define ARC_SUFFIX_NONE (1 << 0)
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#define ARC_SUFFIX_COND (1 << 1)
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#define ARC_SUFFIX_FLAG (1 << 2)
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#define ARC_REGISTER_READONLY (1 << 0)
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#define ARC_REGISTER_WRITEONLY (1 << 1)
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#define ARC_REGISTER_NOSHORT_CUT (1 << 2)
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/* Constants needed to initialize extension instructions. */
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extern const unsigned char flags_none[MAX_INSN_FLGS + 1];
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extern const unsigned char flags_f[MAX_INSN_FLGS + 1];
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extern const unsigned char flags_cc[MAX_INSN_FLGS + 1];
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extern const unsigned char flags_ccf[MAX_INSN_FLGS + 1];
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extern const unsigned char arg_none[MAX_INSN_ARGS + 1];
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extern const unsigned char arg_32bit_rarbrc[MAX_INSN_ARGS + 1];
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extern const unsigned char arg_32bit_zarbrc[MAX_INSN_ARGS + 1];
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extern const unsigned char arg_32bit_rbrbrc[MAX_INSN_ARGS + 1];
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extern const unsigned char arg_32bit_rarbu6[MAX_INSN_ARGS + 1];
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extern const unsigned char arg_32bit_zarbu6[MAX_INSN_ARGS + 1];
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extern const unsigned char arg_32bit_rbrbu6[MAX_INSN_ARGS + 1];
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extern const unsigned char arg_32bit_rbrbs12[MAX_INSN_ARGS + 1];
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extern const unsigned char arg_32bit_ralimmrc[MAX_INSN_ARGS + 1];
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extern const unsigned char arg_32bit_rarblimm[MAX_INSN_ARGS + 1];
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extern const unsigned char arg_32bit_zalimmrc[MAX_INSN_ARGS + 1];
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extern const unsigned char arg_32bit_zarblimm[MAX_INSN_ARGS + 1];
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extern const unsigned char arg_32bit_rbrblimm[MAX_INSN_ARGS + 1];
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extern const unsigned char arg_32bit_ralimmu6[MAX_INSN_ARGS + 1];
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extern const unsigned char arg_32bit_zalimmu6[MAX_INSN_ARGS + 1];
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|
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extern const unsigned char arg_32bit_zalimms12[MAX_INSN_ARGS + 1];
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extern const unsigned char arg_32bit_ralimmlimm[MAX_INSN_ARGS + 1];
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extern const unsigned char arg_32bit_zalimmlimm[MAX_INSN_ARGS + 1];
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extern const unsigned char arg_32bit_rbrc[MAX_INSN_ARGS + 1];
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extern const unsigned char arg_32bit_zarc[MAX_INSN_ARGS + 1];
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extern const unsigned char arg_32bit_rbu6[MAX_INSN_ARGS + 1];
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extern const unsigned char arg_32bit_zau6[MAX_INSN_ARGS + 1];
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extern const unsigned char arg_32bit_rblimm[MAX_INSN_ARGS + 1];
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extern const unsigned char arg_32bit_zalimm[MAX_INSN_ARGS + 1];
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extern const unsigned char arg_32bit_limmrc[MAX_INSN_ARGS + 1];
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extern const unsigned char arg_32bit_limmu6[MAX_INSN_ARGS + 1];
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extern const unsigned char arg_32bit_limms12[MAX_INSN_ARGS + 1];
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extern const unsigned char arg_32bit_limmlimm[MAX_INSN_ARGS + 1];
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|
|
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extern const unsigned char arg_32bit_rc[MAX_INSN_ARGS + 1];
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|
extern const unsigned char arg_32bit_u6[MAX_INSN_ARGS + 1];
|
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extern const unsigned char arg_32bit_limm[MAX_INSN_ARGS + 1];
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/* Address types used in the NPS-400. See page 367 of the NPS-400 CTOP
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Instruction Set Reference Manual v2.4 for a description of address types. */
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typedef enum
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{
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/* Addresses in memory. */
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/* Buffer descriptor. */
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ARC_NPS400_ADDRTYPE_BD,
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/* Job identifier. */
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ARC_NPS400_ADDRTYPE_JID,
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|
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/* Linked Buffer Descriptor. */
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ARC_NPS400_ADDRTYPE_LBD,
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|
|
|
/* Multicast Buffer Descriptor. */
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ARC_NPS400_ADDRTYPE_MBD,
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|
|
|
/* Summarized Address. */
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ARC_NPS400_ADDRTYPE_SD,
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|
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/* SMEM Security Context Local Memory. */
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ARC_NPS400_ADDRTYPE_SM,
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|
|
|
/* Extended Address. */
|
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ARC_NPS400_ADDRTYPE_XA,
|
|
|
|
/* Extended Summarized Address. */
|
|
ARC_NPS400_ADDRTYPE_XD,
|
|
|
|
/* CMEM offset addresses. */
|
|
|
|
/* On-demand Counter Descriptor. */
|
|
ARC_NPS400_ADDRTYPE_CD,
|
|
|
|
/* CMEM Buffer Descriptor. */
|
|
ARC_NPS400_ADDRTYPE_CBD,
|
|
|
|
/* CMEM Job Identifier. */
|
|
ARC_NPS400_ADDRTYPE_CJID,
|
|
|
|
/* CMEM Linked Buffer Descriptor. */
|
|
ARC_NPS400_ADDRTYPE_CLBD,
|
|
|
|
/* CMEM Offset. */
|
|
ARC_NPS400_ADDRTYPE_CM,
|
|
|
|
/* CMEM Summarized Address. */
|
|
ARC_NPS400_ADDRTYPE_CSD,
|
|
|
|
/* CMEM Extended Address. */
|
|
ARC_NPS400_ADDRTYPE_CXA,
|
|
|
|
/* CMEM Extended Summarized Address. */
|
|
ARC_NPS400_ADDRTYPE_CXD
|
|
|
|
} arc_nps_address_type;
|
|
|
|
#define ARC_NUM_ADDRTYPES 16
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif /* OPCODE_ARC_H */
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