Nick Clifton 634a9f67d9 Update the RX simulator to handle the latest opcode types. ... * rx.c (id_names): Add nop4, nop5, nop6 and nop7. (decode_opcode): Likewise. (get_op): Handle RX_Operand_Zero_Indirect. Handle RX_Bad_Size and RX_MAX_SIZE. (put_op): Likewise. (N_MAP): Increase to 90.		2015-11-10 16:08:35 +00:00
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arm
avr
bfin	sim: bfin: handle negative left saturated shifts as ashifts [BZ #18407]	2015-10-11 03:42:09 -04:00
common
cr16	sim: cr16/d10v: localize translation funcs	2015-11-10 02:17:15 -05:00
cris
d10v	sim: cr16/d10v: localize translation funcs	2015-11-10 02:17:15 -05:00
erc32
frv
ft32	sim: ft32: correct simulation of MEMCPY and MEMSET	2015-09-29 23:39:24 -04:00
h8300	sim: h8300: drop unused littleendian variable	2015-11-10 00:07:22 -05:00
igen
iq2000
lm32
m32c	sim: m32c: move test code to testsuite	2015-11-10 00:19:49 -05:00
m32r
m68hc11
mcore
microblaze
mips
mn10300
moxie	sim: moxie: fix leakage in error path [BZ #18273]	2015-10-11 03:56:22 -04:00
msp430
ppc
rl78
rx	Update the RX simulator to handle the latest opcode types.	2015-11-10 16:08:35 +00:00
sh
sh64
testsuite	sim: m32c: move test code to testsuite	2015-11-10 00:19:49 -05:00
v850
.gitignore
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configure
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