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https://sourceware.org/git/binutils-gdb.git
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ac2df442ac
* elf64-ppc.c (ADDI_R12_R12, LD_R11_0R2, LD_R2_0R2): Define. Update stub comments. (build_plt_stub): Build two variants, one without "addis". (ppc_build_one_stub): Build stubs without "addis" if possible. (ppc_size_one_stub): Size new stubs. ld/testsuite/ * ld-powerpc/relbrlt.s (.text.pad2): Adjust space. * ld-powerpc/relbrlt.d: Update. * ld-powerpc/tlsexe.d: Update. * ld-powerpc/tlsexe.g: Update. * ld-powerpc/tlsexe.r: Update. * ld-powerpc/tlsexetoc.d: Update. * ld-powerpc/tlsexetoc.g: Update. * ld-powerpc/tlsexetoc.r: Update. * ld-powerpc/tlsso.d: Update. * ld-powerpc/tlsso.g: Update. * ld-powerpc/tlsso.r: Update. * ld-powerpc/tlstocso.d: Update. * ld-powerpc/tlstocso.g: Update.
49 lines
1.2 KiB
Makefile
49 lines
1.2 KiB
Makefile
#source: relbrlt.s
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#as: -a64
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#ld: -melf64ppc --emit-relocs
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#objdump: -dr
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.*: file format elf64-powerpc
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Disassembly of section \.text:
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0*100000b0 <_start>:
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[0-9a-f ]*: 49 bf 00 2d bl .*
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[0-9a-f ]*: R_PPC64_REL24 \.text\+0x37e003c
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[0-9a-f ]*: 60 00 00 00 nop
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[0-9a-f ]*: 49 bf 00 19 bl .*
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[0-9a-f ]*: R_PPC64_REL24 \.text\+0x3bf0020
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[0-9a-f ]*: 60 00 00 00 nop
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[0-9a-f ]*: 49 bf 00 21 bl .*
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[0-9a-f ]*: R_PPC64_REL24 \.text\+0x57e0024
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[0-9a-f ]*: 60 00 00 00 nop
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[0-9a-f ]*: 00 00 00 00 \.long 0x0
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[0-9a-f ]*: 4b ff ff e4 b .* <_start>
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\.\.\.
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[0-9a-f ]*<.*plt_branch.*>:
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[0-9a-f ]*: e9 62 80 00 ld r11,-32768\(r2\)
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[0-9a-f ]*: 7d 69 03 a6 mtctr r11
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[0-9a-f ]*: 4e 80 04 20 bctr
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[0-9a-f ]*<.*long_branch.*>:
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[0-9a-f ]*: 49 bf 00 10 b .* <far>
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[0-9a-f ]*: R_PPC64_REL24 \*ABS\*\+0x137e00ec
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[0-9a-f ]*<.*plt_branch.*>:
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[0-9a-f ]*: e9 62 80 08 ld r11,-32760\(r2\)
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[0-9a-f ]*: 7d 69 03 a6 mtctr r11
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[0-9a-f ]*: 4e 80 04 20 bctr
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\.\.\.
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0*137e00ec <far>:
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[0-9a-f ]*: 4e 80 00 20 blr
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\.\.\.
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[0-9a-f ]*<far2far>:
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[0-9a-f ]*: 4e 80 00 20 blr
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\.\.\.
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[0-9a-f ]*<huge>:
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[0-9a-f ]*: 4e 80 00 20 blr
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