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6ce26ac7c3
This patch adds support for OpenRISC 64-bit FPU operations on 32-bit cores by using register pairs. The functionality has been added to OpenRISC architecture specification version 1.3 as per architecture proposal 14[0]. For supporting assembly of both 64-bit and 32-bit precision instructions we have defined CGEN_VALIDATE_INSN_SUPPORTED. This allows cgen to use 64-bit bit architecture assembly parsing on 64-bit toolchains and 32-bit architecture assembly parsing on 32-bit toolchains. Without this the assembler has issues parsing register pairs. This patch also contains a few fixes to the symantics for existing OpenRISC single and double precision FPU operations. [0] https://openrisc.io/proposals/orfpx64a32 cpu/ChangeLog: yyyy-mm-dd Andrey Bacherov <avbacherov@opencores.org> Stafford Horne <shorne@gmail.com> * or1k.cpu (ORFPX64A32-MACHS): New pmacro. (ORFPX-MACHS): Removed pmacro. * or1k.opc (or1k_cgen_insn_supported): New function. (CGEN_VALIDATE_INSN_SUPPORTED): Define macro. (parse_regpair, print_regpair): New functions. * or1kcommon.cpu (h-spr, spr-shift, spr-address, h-gpr): Reorder and add comments. (h-fdr): Update comment to indicate or64. (reg-pair-reg-lo, reg-pair-reg-hi): New pmacros for register pairs. (h-fd32r): New hardware for 64-bit fpu registers. (h-i64r): New hardware for 64-bit int registers. * or1korbis.cpu (f-resv-8-1): New field. * or1korfpx.cpu (rDSF, rASF, rBSF): Update attribute to ORFPX32-MACHS. (rDDF, rADF, rBDF): Update operand comment to indicate or64. (f-rdoff-10-1, f-raoff-9-1, f-rboff-8-1): New fields. (h-roff1): New hardware. (double-field-and-ops mnemonic): New pmacro to generate operations rDD32F, rAD32F, rBD32F, rDDI and rADI. (float-regreg-insn): Update single precision generator to MACH ORFPX32-MACHS. Add generator for or32 64-bit instructions. (float-setflag-insn): Update single precision generator to MACH ORFPX32-MACHS. Fix double instructions from single to double precision. Add generator for or32 64-bit instructions. (float-cust-insn cust-num): Update single precision generator to MACH ORFPX32-MACHS. Add generator for or32 64-bit instructions. (lf-rem-s, lf-itof-s, lf-ftoi-s, lf-madd-s): Update MACH to ORFPX32-MACHS. (lf-rem-d): Fix operation from mod to rem. (lf-rem-d32, lf-itof-d32, lf-ftoi-d32, lf-madd-d32): New instruction. (lf-itof-d): Fix operands from single to double. (lf-ftoi-d): Update operand mode from DI to WI.
515 lines
12 KiB
C
515 lines
12 KiB
C
/* OpenRISC 1000 opcode support. -*- C -*-
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Copyright 2000-2014 Free Software Foundation, Inc.
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Originally ontributed for OR32 by Red Hat Inc;
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This file is part of the GNU Binutils.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, see <http://www.gnu.org/licenses/>. */
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/* This file is an addendum to or1k.cpu. Heavy use of C code isn't
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appropriate in .cpu files, so it resides here. This especially applies
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to assembly/disassembly where parsing/printing can be quite involved.
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Such things aren't really part of the specification of the cpu, per se,
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so .cpu files provide the general framework and .opc files handle the
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nitty-gritty details as necessary.
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Each section is delimited with start and end markers.
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<arch>-opc.h additions use: "-- opc.h"
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<arch>-opc.c additions use: "-- opc.c"
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<arch>-asm.c additions use: "-- asm.c"
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<arch>-dis.c additions use: "-- dis.c"
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<arch>-ibd.h additions use: "-- ibd.h" */
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/* -- opc.h */
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#undef CGEN_DIS_HASH_SIZE
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#define CGEN_DIS_HASH_SIZE 256
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#undef CGEN_DIS_HASH
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#define CGEN_DIS_HASH(buffer, value) (((unsigned char *) (buffer))[0] >> 2)
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/* Check applicability of instructions against machines. */
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#define CGEN_VALIDATE_INSN_SUPPORTED
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extern int or1k_cgen_insn_supported (CGEN_CPU_DESC, const CGEN_INSN *);
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/* -- */
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/* -- opc.c */
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/* Special check to ensure that instruction exists for given machine. */
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int
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or1k_cgen_insn_supported (CGEN_CPU_DESC cd, const CGEN_INSN *insn)
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{
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int machs = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_MACH);
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/* No mach attribute? Assume it's supported for all machs. */
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if (machs == 0)
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return 1;
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return ((machs & cd->machs) != 0);
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}
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/* -- */
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/* -- asm.c */
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static const char * MISSING_CLOSING_PARENTHESIS = N_("missing `)'");
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static const char * INVALID_STORE_RELOC = N_("relocation invalid for store");
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static const char * INVALID_RELOC_TYPE = N_("internal relocation type invalid");
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#define CGEN_VERBOSE_ASSEMBLER_ERRORS
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static const char *
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parse_disp26 (CGEN_CPU_DESC cd,
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const char ** strp,
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int opindex,
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int opinfo ATTRIBUTE_UNUSED,
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enum cgen_parse_operand_result * resultp,
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bfd_vma * valuep)
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{
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const char *str = *strp;
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const char *errmsg = NULL;
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bfd_reloc_code_real_type reloc = BFD_RELOC_OR1K_REL_26;
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if (strncasecmp (str, "plta(", 5) == 0)
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{
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*strp = str + 5;
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reloc = BFD_RELOC_OR1K_PLTA26;
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}
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else if (strncasecmp (str, "plt(", 4) == 0)
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{
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*strp = str + 4;
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reloc = BFD_RELOC_OR1K_PLT26;
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}
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errmsg = cgen_parse_address (cd, strp, opindex, reloc, resultp, valuep);
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if (reloc != BFD_RELOC_OR1K_REL_26)
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{
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if (**strp != ')')
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errmsg = MISSING_CLOSING_PARENTHESIS;
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else
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++*strp;
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}
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return errmsg;
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}
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static const char *
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parse_disp21 (CGEN_CPU_DESC cd,
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const char ** strp,
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int opindex,
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int opinfo ATTRIBUTE_UNUSED,
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enum cgen_parse_operand_result * resultp,
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bfd_vma * valuep)
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{
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const char *str = *strp;
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const char *errmsg = NULL;
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bfd_reloc_code_real_type reloc = BFD_RELOC_OR1K_PCREL_PG21;
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if (strncasecmp (str, "got(", 4) == 0)
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{
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*strp = str + 4;
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reloc = BFD_RELOC_OR1K_GOT_PG21;
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}
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else if (strncasecmp (str, "tlsgd(", 6) == 0)
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{
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*strp = str + 6;
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reloc = BFD_RELOC_OR1K_TLS_GD_PG21;
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}
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else if (strncasecmp (str, "tlsldm(", 7) == 0)
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{
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*strp = str + 7;
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reloc = BFD_RELOC_OR1K_TLS_LDM_PG21;
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}
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else if (strncasecmp (str, "gottp(", 6) == 0)
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{
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*strp = str + 6;
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reloc = BFD_RELOC_OR1K_TLS_IE_PG21;
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}
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errmsg = cgen_parse_address (cd, strp, opindex, reloc, resultp, valuep);
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if (reloc != BFD_RELOC_OR1K_PCREL_PG21)
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{
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if (**strp != ')')
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errmsg = MISSING_CLOSING_PARENTHESIS;
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else
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++*strp;
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}
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return errmsg;
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}
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enum or1k_rclass
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{
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RCLASS_DIRECT = 0,
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RCLASS_GOT = 1,
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RCLASS_GOTPC = 2,
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RCLASS_GOTOFF = 3,
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RCLASS_TLSGD = 4,
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RCLASS_TLSLDM = 5,
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RCLASS_DTPOFF = 6,
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RCLASS_GOTTPOFF = 7,
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RCLASS_TPOFF = 8,
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};
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enum or1k_rtype
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{
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RTYPE_LO = 0,
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RTYPE_SLO = 1,
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RTYPE_PO = 2,
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RTYPE_SPO = 3,
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RTYPE_HI = 4,
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RTYPE_AHI = 5,
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};
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#define RCLASS_SHIFT 3
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#define RTYPE_MASK 7
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static const bfd_reloc_code_real_type or1k_imm16_relocs[][6] = {
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{ BFD_RELOC_LO16,
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BFD_RELOC_OR1K_SLO16,
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BFD_RELOC_OR1K_LO13,
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BFD_RELOC_OR1K_SLO13,
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BFD_RELOC_HI16,
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BFD_RELOC_HI16_S, },
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{ BFD_RELOC_OR1K_GOT16,
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BFD_RELOC_UNUSED,
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BFD_RELOC_OR1K_GOT_LO13,
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BFD_RELOC_UNUSED,
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BFD_RELOC_UNUSED,
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BFD_RELOC_UNUSED },
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{ BFD_RELOC_OR1K_GOTPC_LO16,
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BFD_RELOC_UNUSED,
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BFD_RELOC_UNUSED,
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BFD_RELOC_UNUSED,
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BFD_RELOC_OR1K_GOTPC_HI16,
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BFD_RELOC_UNUSED },
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{ BFD_RELOC_LO16_GOTOFF,
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BFD_RELOC_OR1K_GOTOFF_SLO16,
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BFD_RELOC_UNUSED,
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BFD_RELOC_UNUSED,
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BFD_RELOC_HI16_GOTOFF,
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BFD_RELOC_HI16_S_GOTOFF },
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{ BFD_RELOC_OR1K_TLS_GD_LO16,
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BFD_RELOC_UNUSED,
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BFD_RELOC_OR1K_TLS_GD_LO13,
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BFD_RELOC_UNUSED,
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BFD_RELOC_OR1K_TLS_GD_HI16,
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BFD_RELOC_UNUSED },
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{ BFD_RELOC_OR1K_TLS_LDM_LO16,
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BFD_RELOC_UNUSED,
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BFD_RELOC_OR1K_TLS_LDM_LO13,
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BFD_RELOC_UNUSED,
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BFD_RELOC_OR1K_TLS_LDM_HI16,
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BFD_RELOC_UNUSED },
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{ BFD_RELOC_OR1K_TLS_LDO_LO16,
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BFD_RELOC_UNUSED,
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BFD_RELOC_UNUSED,
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BFD_RELOC_UNUSED,
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BFD_RELOC_OR1K_TLS_LDO_HI16,
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BFD_RELOC_UNUSED },
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{ BFD_RELOC_OR1K_TLS_IE_LO16,
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BFD_RELOC_UNUSED,
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BFD_RELOC_OR1K_TLS_IE_LO13,
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BFD_RELOC_UNUSED,
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BFD_RELOC_OR1K_TLS_IE_HI16,
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BFD_RELOC_OR1K_TLS_IE_AHI16 },
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{ BFD_RELOC_OR1K_TLS_LE_LO16,
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BFD_RELOC_OR1K_TLS_LE_SLO16,
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BFD_RELOC_UNUSED,
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BFD_RELOC_UNUSED,
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BFD_RELOC_OR1K_TLS_LE_HI16,
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BFD_RELOC_OR1K_TLS_LE_AHI16 },
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};
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static int
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parse_reloc (const char **strp)
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{
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const char *str = *strp;
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enum or1k_rclass cls = RCLASS_DIRECT;
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enum or1k_rtype typ;
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if (strncasecmp (str, "got(", 4) == 0)
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{
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*strp = str + 4;
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return (RCLASS_GOT << RCLASS_SHIFT) | RTYPE_LO;
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}
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if (strncasecmp (str, "gotpo(", 6) == 0)
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{
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*strp = str + 6;
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return (RCLASS_GOT << RCLASS_SHIFT) | RTYPE_PO;
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}
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if (strncasecmp (str, "gottppo(", 8) == 0)
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{
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*strp = str + 8;
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return (RCLASS_GOTTPOFF << RCLASS_SHIFT) | RTYPE_PO;
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}
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if (strncasecmp (str, "gotpc", 5) == 0)
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{
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str += 5;
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cls = RCLASS_GOTPC;
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}
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else if (strncasecmp (str, "gotoff", 6) == 0)
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{
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str += 6;
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cls = RCLASS_GOTOFF;
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}
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else if (strncasecmp (str, "tlsgd", 5) == 0)
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{
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str += 5;
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cls = RCLASS_TLSGD;
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}
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else if (strncasecmp (str, "tlsldm", 6) == 0)
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{
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str += 6;
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cls = RCLASS_TLSLDM;
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}
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else if (strncasecmp (str, "dtpoff", 6) == 0)
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{
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str += 6;
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cls = RCLASS_DTPOFF;
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}
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else if (strncasecmp (str, "gottpoff", 8) == 0)
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{
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str += 8;
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cls = RCLASS_GOTTPOFF;
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}
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else if (strncasecmp (str, "tpoff", 5) == 0)
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{
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str += 5;
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cls = RCLASS_TPOFF;
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}
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if (strncasecmp (str, "hi(", 3) == 0)
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{
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str += 3;
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typ = RTYPE_HI;
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}
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else if (strncasecmp (str, "lo(", 3) == 0)
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{
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str += 3;
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typ = RTYPE_LO;
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}
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else if (strncasecmp (str, "ha(", 3) == 0)
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{
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str += 3;
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typ = RTYPE_AHI;
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}
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else if (strncasecmp (str, "po(", 3) == 0 && cls != RCLASS_GOTTPOFF)
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{
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str += 3;
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typ = RTYPE_PO;
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}
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else
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return -1;
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*strp = str;
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return (cls << RCLASS_SHIFT) | typ;
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}
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static const char *
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parse_imm16 (CGEN_CPU_DESC cd, const char **strp, int opindex,
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long *valuep, int splitp)
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{
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const char *errmsg;
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enum cgen_parse_operand_result result_type;
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bfd_reloc_code_real_type reloc = BFD_RELOC_UNUSED;
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enum or1k_rtype reloc_type;
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int reloc_code;
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bfd_vma ret;
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if (**strp == '#')
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++*strp;
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reloc_code = parse_reloc (strp);
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reloc_type = reloc_code & RTYPE_MASK;
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if (reloc_code >= 0)
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{
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enum or1k_rclass reloc_class = reloc_code >> RCLASS_SHIFT;
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if (splitp)
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{
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if ((reloc_type == RTYPE_LO || reloc_type == RTYPE_PO)
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&& reloc_class != RCLASS_GOT)
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/* If split we or up the type to RTYPE_SLO or RTYPE_SPO. */
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reloc_type |= 1;
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else
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return INVALID_STORE_RELOC;
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}
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reloc = or1k_imm16_relocs[reloc_class][reloc_type];
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}
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if (reloc != BFD_RELOC_UNUSED)
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{
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bfd_vma value;
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errmsg = cgen_parse_address (cd, strp, opindex, reloc,
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&result_type, &value);
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if (**strp != ')')
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errmsg = MISSING_CLOSING_PARENTHESIS;
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++*strp;
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ret = value;
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if (errmsg == NULL && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
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switch (reloc_type)
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{
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case RTYPE_AHI:
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ret += 0x8000;
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/* FALLTHRU */
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case RTYPE_HI:
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ret >>= 16;
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/* FALLTHRU */
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case RTYPE_LO:
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case RTYPE_SLO:
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ret &= 0xffff;
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ret = (ret ^ 0x8000) - 0x8000;
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break;
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case RTYPE_PO:
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case RTYPE_SPO:
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ret &= 0x1fff;
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break;
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default:
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errmsg = INVALID_RELOC_TYPE;
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}
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}
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else
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{
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long value;
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errmsg = cgen_parse_signed_integer (cd, strp, opindex, &value);
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ret = value;
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}
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if (errmsg == NULL)
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*valuep = ret;
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return errmsg;
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}
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static const char *
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parse_simm16 (CGEN_CPU_DESC cd, const char **strp, int opindex, long *valuep)
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{
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return parse_imm16(cd, strp, opindex, (long *) valuep, 0);
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}
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static const char *
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parse_simm16_split (CGEN_CPU_DESC cd, const char **strp, int opindex,
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long *valuep)
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{
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return parse_imm16(cd, strp, opindex, (long *) valuep, 1);
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}
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static const char *
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parse_uimm16 (CGEN_CPU_DESC cd, const char **strp, int opindex,
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unsigned long *valuep)
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{
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const char *errmsg = parse_imm16(cd, strp, opindex, (long *) valuep, 0);
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if (errmsg == NULL)
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*valuep &= 0xffff;
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return errmsg;
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}
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static const char *
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parse_uimm16_split (CGEN_CPU_DESC cd, const char **strp, int opindex,
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unsigned long *valuep)
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{
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const char *errmsg = parse_imm16(cd, strp, opindex, (long *) valuep, 1);
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if (errmsg == NULL)
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*valuep &= 0xffff;
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return errmsg;
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}
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/* Parse register pairs with syntax rA,rB to a flag + rA value. */
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static const char *
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parse_regpair (CGEN_CPU_DESC cd, const char **strp,
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int opindex ATTRIBUTE_UNUSED, unsigned long *valuep)
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{
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long reg1_index;
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long reg2_index;
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const char *errmsg;
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/* The first part should just be a register. */
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errmsg = cgen_parse_keyword (cd, strp, &or1k_cgen_opval_h_gpr,
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®1_index);
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/* If that worked skip the comma separator. */
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if (errmsg == NULL)
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|
{
|
|
if (**strp == ',')
|
|
++*strp;
|
|
else
|
|
errmsg = "Unexpected character, expected ','";
|
|
}
|
|
|
|
/* If that worked the next part is just another register. */
|
|
if (errmsg == NULL)
|
|
errmsg = cgen_parse_keyword (cd, strp, &or1k_cgen_opval_h_gpr,
|
|
®2_index);
|
|
|
|
/* Validate the register pair is valid and create the output value. */
|
|
if (errmsg == NULL)
|
|
{
|
|
int regoffset = reg2_index - reg1_index;
|
|
|
|
if (regoffset == 1 || regoffset == 2)
|
|
{
|
|
unsigned short offsetmask;
|
|
unsigned short value;
|
|
|
|
offsetmask = ((regoffset == 2 ? 1 : 0) << 5);
|
|
value = offsetmask | reg1_index;
|
|
|
|
*valuep = value;
|
|
}
|
|
else
|
|
errmsg = "Invalid register pair, offset not 1 or 2.";
|
|
}
|
|
|
|
return errmsg;
|
|
}
|
|
|
|
/* -- */
|
|
|
|
/* -- dis.c */
|
|
|
|
static void
|
|
print_regpair (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
|
|
void * dis_info,
|
|
long value,
|
|
unsigned int attrs ATTRIBUTE_UNUSED,
|
|
bfd_vma pc ATTRIBUTE_UNUSED,
|
|
int length ATTRIBUTE_UNUSED)
|
|
{
|
|
disassemble_info *info = dis_info;
|
|
char reg1_index;
|
|
char reg2_index;
|
|
|
|
reg1_index = value & 0x1f;
|
|
reg2_index = reg1_index + ((value & (1 << 5)) ? 2 : 1);
|
|
|
|
(*info->fprintf_func) (info->stream, "r%d,r%d", reg1_index, reg2_index);
|
|
}
|
|
|
|
/* -- */
|
|
|
|
/* -- ibd.h */
|
|
|
|
/* -- */
|