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binutils-gdb/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-mips16.od
Simon Dardis 40fc1451c6 [MIPS] Map 'move' to 'or'. 
The MIPS assembly idiom 'move' now maps to the 'or' machine instruction. This
change affects microMIPS, MIPS32, MIPS64.

2015-08-12  Simon Dardis  <simon.dardis@imgtec.com>

opcodes/

	* micromips-opc.c (micromips_opcodes): Re-order table so that move
	based on 'or' is first.
	* mips-opc.c (mips_builtin_opcodes): Ditto.

bfd/

	* elfxx-mips.c (STUB_MOVE): Change to use 'or' only.
	(mips_o32_exec_plt0_entry, mips_n32_exec_plt0_entry,
	mips_n64_exec_plt0_entry, micromips_insn32_o32_exec_plt0_entry):
	Update to use 'or' instead of 'addu/daddu'.
	(_bfd_mips_elf_finish_dynamic_symbol): Update usage of STUB_MOVE.
	(move_insns_32): Reorder table.

gas/

	* config/tc-mips.c (move_register): Change to use 'or' only.
	(s_cpload, s_cpsetup, s_cprestore, s_cpreturn): Update to
	use or for move.

gas/testsuite/

	* gas/mips/elf-rel23.d: Update test.
	* gas/mips/elf-rel23.d: Ditto.
	* gas/mips/elf-rel23a.d: Ditto.
	* gas/mips/elf-rel23b.d: Ditto.
	* gas/mips/elf_e_flags1.d: Ditto.
	* gas/mips/elf_e_flags2.d: Ditto.
	* gas/mips/elf_e_flags3.d: Ditto.
	* gas/mips/elf_e_flags4.d: Ditto.
	* gas/mips/loc-swap-dis.d: Ditto.
	* gas/mips/micromips-insn32.d: Ditto.
	* gas/mips/micromips-noinsn32.d: Ditto.
	* gas/mips/micromips-trap.d: Ditto.
	* gas/mips/micromips.d: Ditto.
	* gas/mips/mips-abi32-pic.d: Ditto.
	* gas/mips/mips-abi32.d: Ditto.
	* gas/mips/mips-gp32-fp32-pic.d: Ditto.
	* gas/mips/mips-gp32-fp32.d: Ditto.
	* gas/mips/mips-gp32-fp64-pic.d: Ditto.
	* gas/mips/mips-gp32-fp64.d: Ditto.
	* gas/mips/mips-gp64-fp32-pic.d: Ditto.
	* gas/mips/mips-gp64-fp32.d: Ditto.
	* gas/mips/mips-gp64-fp64-pic.d: Ditto.
	* gas/mips/mips-gp64-fp64.d: Ditto.
	* gas/mips/mipsr6@loc-swap-dis.d: Ditto.
	* gas/mips/tls-o32.d: Ditto.
	* gas/mips/uld2-eb.d: Ditto.
	* gas/mips/uld2-el.d: Ditto.
	* gas/mips/ulw2-eb-ilocks.d: Ditto.
	* gas/mips/ulw2-eb.d: Ditto.
	* gas/mips/ulw2-el-ilocks.d: Ditto.
	* gas/mips/ulw2-el.d: Ditto.
	* gas/mips/move.d: New test.
	* gas/mips/move.s: Ditto.
	* gas/mips/micromips32-move.d: Ditto.
	* gas/mips/micromips32-move.s: Ditto.
	* gas/mips/mips.exp: Run the new tests.

gold/

	* mips.cc (plt0_entry_o32, plt0_entry_n32, plt0_entry_n64,
	lazy_stub_normal_1, lazy_stub_normal_1_n64,
	lazy_stub_normal_2, lazy_stub_normal_2_n64, lazy_stub_big,
	lazy_stub_big_n64, lazy_stub_micromips32_normal_1_n64,
	lazy_stub_micromips32_normal_2_n64, lazy_stub_micromips32_big,
	lazy_stub_micromips32_big_n64): Update to use 'or' for move instead
	of 'addu/daddu'.

ld/testsuite/

	* ld-mips-elf/compressed-plt-1-n32-mips16.od: Update test.
	* ld-mips-elf/compressed-plt-1-n32-umips.od: Ditto.
	* ld-mips-elf/compressed-plt-1-o32-mips16-got.od: Ditto.
	* ld-mips-elf/compressed-plt-1-o32-mips16-only.od: Ditto.
	* ld-mips-elf/compressed-plt-1-o32-mips16-word.od: Ditto.
	* ld-mips-elf/compressed-plt-1-o32-mips16.od: Ditto.
	* ld-mips-elf/compressed-plt-1-o32-se.od: Ditto.
	* ld-mips-elf/compressed-plt-1-o32-umips-got.od: Ditto.
	* ld-mips-elf/compressed-plt-1-o32-umips-word.od: Ditto.
	* ld-mips-elf/compressed-plt-1-o32-umips.od: Ditto.
	* ld-mips-elf/jalx-2.dd: Ditto.
	* ld-mips-elf/mips16-pic-3.dd: Ditto.
	* ld-mips-elf/pic-and-nonpic-3a.dd: Ditto.
	* ld-mips-elf/pic-and-nonpic-3b.dd: Ditto.
	* ld-mips-elf/pic-and-nonpic-5b.dd: Ditto.
	* ld-mips-elf/pic-and-nonpic-6-n32.dd: Ditto.
	* ld-mips-elf/pic-and-nonpic-6-o32.dd: Ditto.
	* ld-mips-elf/stub-dynsym-1-10000.d: Ditto.
	* ld-mips-elf/stub-dynsym-1-2fe80.d: Ditto.
	* ld-mips-elf/stub-dynsym-1-7fff.d: Ditto.
	* ld-mips-elf/stub-dynsym-1-8000.d: Ditto.
	* ld-mips-elf/stub-dynsym-1-fff0.d: Ditto.
	* ld-mips-elf/tlsbin-o32.d: Ditto.
	* ld-mips-elf/tlsdyn-o32-1.d: Ditto.
	* ld-mips-elf/tlsdyn-o32-2.d: Ditto.
	* ld-mips-elf/tlsdyn-o32-3.d: Ditto.
	* ld-mips-elf/tlsdyn-o32.d: Ditto.
	* ld-mips-elf/tlslib-o32.d: Ditto.
2015-08-12 17:10:22 +01:00

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.* file format .*
Disassembly of section \.plt:
# Only _dc (direct call from compressed code) functions should have a
# MIPS16 PLT. Note that indirect calls do not influence the choice,
# so f_ic and f_lo_ic have MIPS rather than MIPS16 PLTs.
10100000 <_PROCEDURE_LINKAGE_TABLE_>:
.*: 3c1c1020 lui \$28,0x1020
.*: 8f990000 lw \$25,0\(\$28\)
.*: 279c0000 addiu \$28,\$28,0
.*: 031cc023 subu \$24,\$24,\$28
.*: 03e07825 move \$15,\$31
.*: 0018c082 srl \$24,\$24,0x2
.*: 0320f809 jalr \$25
.*: 2718fffe addiu \$24,\$24,-2
10100020 <f_lo_iu@plt>:
.*: 3c0f1020 lui \$15,0x1020
.*: 8df90008 lw \$25,8\(\$15\)
.*: 03200008 jr \$25
.*: 25f80008 addiu \$24,\$15,8
10100030 <f_lo_iu_du_dc@plt>:
.*: 3c0f1020 lui \$15,0x1020
.*: 8df9000c lw \$25,12\(\$15\)
.*: 03200008 jr \$25
.*: 25f8000c addiu \$24,\$15,12
10100040 <f_lo_du_ic_dc@plt>:
.*: 3c0f1020 lui \$15,0x1020
.*: 8df90010 lw \$25,16\(\$15\)
.*: 03200008 jr \$25
.*: 25f80010 addiu \$24,\$15,16
10100050 <f_du_dc@plt>:
.*: 3c0f1020 lui \$15,0x1020
.*: 8df90014 lw \$25,20\(\$15\)
.*: 03200008 jr \$25
.*: 25f80014 addiu \$24,\$15,20
10100060 <f_iu_du_ic@plt>:
.*: 3c0f1020 lui \$15,0x1020
.*: 8df9001c lw \$25,28\(\$15\)
.*: 03200008 jr \$25
.*: 25f8001c addiu \$24,\$15,28
10100070 <f_lo_du_ic@plt>:
.*: 3c0f1020 lui \$15,0x1020
.*: 8df90020 lw \$25,32\(\$15\)
.*: 03200008 jr \$25
.*: 25f80020 addiu \$24,\$15,32
10100080 <f_lo_iu_ic@plt>:
.*: 3c0f1020 lui \$15,0x1020
.*: 8df90028 lw \$25,40\(\$15\)
.*: 03200008 jr \$25
.*: 25f80028 addiu \$24,\$15,40
10100090 <f_lo_ic@plt>:
.*: 3c0f1020 lui \$15,0x1020
.*: 8df9002c lw \$25,44\(\$15\)
.*: 03200008 jr \$25
.*: 25f8002c addiu \$24,\$15,44
101000a0 <f_lo_du_dc@plt>:
.*: 3c0f1020 lui \$15,0x1020
.*: 8df90030 lw \$25,48\(\$15\)
.*: 03200008 jr \$25
.*: 25f80030 addiu \$24,\$15,48
101000b0 <f_du@plt>:
.*: 3c0f1020 lui \$15,0x1020
.*: 8df90034 lw \$25,52\(\$15\)
.*: 03200008 jr \$25
.*: 25f80034 addiu \$24,\$15,52
101000c0 <f_du_ic_dc@plt>:
.*: 3c0f1020 lui \$15,0x1020
.*: 8df90038 lw \$25,56\(\$15\)
.*: 03200008 jr \$25
.*: 25f80038 addiu \$24,\$15,56
101000d0 <f_du_ic@plt>:
.*: 3c0f1020 lui \$15,0x1020
.*: 8df9003c lw \$25,60\(\$15\)
.*: 03200008 jr \$25
.*: 25f8003c addiu \$24,\$15,60
101000e0 <f_iu_du_dc@plt>:
.*: 3c0f1020 lui \$15,0x1020
.*: 8df90040 lw \$25,64\(\$15\)
.*: 03200008 jr \$25
.*: 25f80040 addiu \$24,\$15,64
101000f0 <f_iu_du@plt>:
.*: 3c0f1020 lui \$15,0x1020
.*: 8df90048 lw \$25,72\(\$15\)
.*: 03200008 jr \$25
.*: 25f80048 addiu \$24,\$15,72
10100100 <f_lo_iu_du@plt>:
.*: 3c0f1020 lui \$15,0x1020
.*: 8df9004c lw \$25,76\(\$15\)
.*: 03200008 jr \$25
.*: 25f8004c addiu \$24,\$15,76
10100110 <f_lo_du@plt>:
.*: 3c0f1020 lui \$15,0x1020
.*: 8df90058 lw \$25,88\(\$15\)
.*: 03200008 jr \$25
.*: 25f80058 addiu \$24,\$15,88
10100120 <f_iu_du_ic_dc@plt>:
.*: 3c0f1020 lui \$15,0x1020
.*: 8df90060 lw \$25,96\(\$15\)
.*: 03200008 jr \$25
.*: 25f80060 addiu \$24,\$15,96
10100130 <f_lo_iu_du_ic@plt>:
.*: 3c0f1020 lui \$15,0x1020
.*: 8df90068 lw \$25,104\(\$15\)
.*: 03200008 jr \$25
.*: 25f80068 addiu \$24,\$15,104
10100140 <f_lo_iu_du_ic_dc@plt>:
.*: 3c0f1020 lui \$15,0x1020
.*: 8df9006c lw \$25,108\(\$15\)
.*: 03200008 jr \$25
.*: 25f8006c addiu \$24,\$15,108
10100150 <f_lo@plt>:
.*: 3c0f1020 lui \$15,0x1020
.*: 8df90074 lw \$25,116\(\$15\)
.*: 03200008 jr \$25
.*: 25f80074 addiu \$24,\$15,116
10100160 <f_lo_iu_du_dc@mips16plt>:
.*: b203 lw \$2,1010016c <f_lo_iu_du_dc@mips16plt\+0xc>
.*: 9a60 lw \$3,0\(\$2\)
.*: 651a move \$24,\$2
.*: eb00 jr \$3
.*: 653b move \$25,\$3
.*: 6500 nop
.*: .... .... \.word 0x1020000c
10100170 <f_lo_du_ic_dc@mips16plt>:
.*: b203 lw \$2,1010017c <f_lo_du_ic_dc@mips16plt\+0xc>
.*: 9a60 lw \$3,0\(\$2\)
.*: 651a move \$24,\$2
.*: eb00 jr \$3
.*: 653b move \$25,\$3
.*: 6500 nop
.*: .... .... \.word 0x10200010
10100180 <f_du_dc@mips16plt>:
.*: b203 lw \$2,1010018c <f_du_dc@mips16plt\+0xc>
.*: 9a60 lw \$3,0\(\$2\)
.*: 651a move \$24,\$2
.*: eb00 jr \$3
.*: 653b move \$25,\$3
.*: 6500 nop
.*: .... .... \.word 0x10200014
10100190 <f_lo_iu_dc@mips16plt>:
.*: b203 lw \$2,1010019c <f_lo_iu_dc@mips16plt\+0xc>
.*: 9a60 lw \$3,0\(\$2\)
.*: 651a move \$24,\$2
.*: eb00 jr \$3
.*: 653b move \$25,\$3
.*: 6500 nop
.*: .... .... \.word 0x10200018
101001a0 <f_iu_dc@mips16plt>:
.*: b203 lw \$2,101001ac <f_iu_dc@mips16plt\+0xc>
.*: 9a60 lw \$3,0\(\$2\)
.*: 651a move \$24,\$2
.*: eb00 jr \$3
.*: 653b move \$25,\$3
.*: 6500 nop
.*: .... .... \.word 0x10200024
101001b0 <f_lo_du_dc@mips16plt>:
.*: b203 lw \$2,101001bc <f_lo_du_dc@mips16plt\+0xc>
.*: 9a60 lw \$3,0\(\$2\)
.*: 651a move \$24,\$2
.*: eb00 jr \$3
.*: 653b move \$25,\$3
.*: 6500 nop
.*: .... .... \.word 0x10200030
101001c0 <f_du_ic_dc@mips16plt>:
.*: b203 lw \$2,101001cc <f_du_ic_dc@mips16plt\+0xc>
.*: 9a60 lw \$3,0\(\$2\)
.*: 651a move \$24,\$2
.*: eb00 jr \$3
.*: 653b move \$25,\$3
.*: 6500 nop
.*: .... .... \.word 0x10200038
101001d0 <f_iu_du_dc@mips16plt>:
.*: b203 lw \$2,101001dc <f_iu_du_dc@mips16plt\+0xc>
.*: 9a60 lw \$3,0\(\$2\)
.*: 651a move \$24,\$2
.*: eb00 jr \$3
.*: 653b move \$25,\$3
.*: 6500 nop
.*: .... .... \.word 0x10200040
101001e0 <f_lo_dc@mips16plt>:
.*: b203 lw \$2,101001ec <f_lo_dc@mips16plt\+0xc>
.*: 9a60 lw \$3,0\(\$2\)
.*: 651a move \$24,\$2
.*: eb00 jr \$3
.*: 653b move \$25,\$3
.*: 6500 nop
.*: .... .... \.word 0x10200044
101001f0 <f_dc@mips16plt>:
.*: b203 lw \$2,101001fc <f_dc@mips16plt\+0xc>
.*: 9a60 lw \$3,0\(\$2\)
.*: 651a move \$24,\$2
.*: eb00 jr \$3
.*: 653b move \$25,\$3
.*: 6500 nop
.*: .... .... \.word 0x10200050
10100200 <f_ic_dc@mips16plt>:
.*: b203 lw \$2,1010020c <f_ic_dc@mips16plt\+0xc>
.*: 9a60 lw \$3,0\(\$2\)
.*: 651a move \$24,\$2
.*: eb00 jr \$3
.*: 653b move \$25,\$3
.*: 6500 nop
.*: .... .... \.word 0x10200054
10100210 <f_iu_ic_dc@mips16plt>:
.*: b203 lw \$2,1010021c <f_iu_ic_dc@mips16plt\+0xc>
.*: 9a60 lw \$3,0\(\$2\)
.*: 651a move \$24,\$2
.*: eb00 jr \$3
.*: 653b move \$25,\$3
.*: 6500 nop
.*: .... .... \.word 0x1020005c
10100220 <f_iu_du_ic_dc@mips16plt>:
.*: b203 lw \$2,1010022c <f_iu_du_ic_dc@mips16plt\+0xc>
.*: 9a60 lw \$3,0\(\$2\)
.*: 651a move \$24,\$2
.*: eb00 jr \$3
.*: 653b move \$25,\$3
.*: 6500 nop
.*: .... .... \.word 0x10200060
10100230 <f_lo_iu_ic_dc@mips16plt>:
.*: b203 lw \$2,1010023c <f_lo_iu_ic_dc@mips16plt\+0xc>
.*: 9a60 lw \$3,0\(\$2\)
.*: 651a move \$24,\$2
.*: eb00 jr \$3
.*: 653b move \$25,\$3
.*: 6500 nop
.*: .... .... \.word 0x10200064
10100240 <f_lo_iu_du_ic_dc@mips16plt>:
.*: b203 lw \$2,1010024c <f_lo_iu_du_ic_dc@mips16plt\+0xc>
.*: 9a60 lw \$3,0\(\$2\)
.*: 651a move \$24,\$2
.*: eb00 jr \$3
.*: 653b move \$25,\$3
.*: 6500 nop
.*: .... .... \.word 0x1020006c
10100250 <f_lo_ic_dc@mips16plt>:
.*: b203 lw \$2,1010025c <f_lo_ic_dc@mips16plt\+0xc>
.*: 9a60 lw \$3,0\(\$2\)
.*: 651a move \$24,\$2
.*: eb00 jr \$3
.*: 653b move \$25,\$3
.*: 6500 nop
.*: .... .... \.word 0x10200070
Disassembly of section \.MIPS\.stubs:
10101000 <_MIPS_STUBS_>:
# Lazy-binding stub for f_iu.
.*: 8f998010 lw \$25,-32752\(\$28\)
.*: 03e07825 move \$15,\$31
.*: 0320f809 jalr \$25
.*: 24180021 li \$24,33
# Lazy-binding stub for f_ic.
.*: 8f998010 lw \$25,-32752\(\$28\)
.*: 03e07825 move \$15,\$31
.*: 0320f809 jalr \$25
.*: 24180020 li \$24,32
# Lazy-binding stub for f_iu_ic.
.*: 8f998010 lw \$25,-32752\(\$28\)
.*: 03e07825 move \$15,\$31
.*: 0320f809 jalr \$25
.*: 2418001f li \$24,31
\.\.\.
Disassembly of section \.text\.a:
10102000 <testc>:
.*: .... .... jal [0-9a-f]+ <f_dc@mips16plt>
.*: 6500 nop
.*: f070 9b50 lw \$2,-32656\(\$3\)
# ^ global GOT entry for f_ic
.*: .... .... jal [0-9a-f]+ <f_ic_dc@mips16plt>
.*: 6500 nop
.*: f010 9b58 lw \$2,-32744\(\$3\)
# ^ local GOT entry for f_ic_dc@mips16plt
.*: .... .... jal [0-9a-f]+ <f_du_dc@mips16plt>
.*: 6500 nop
.*: f010 9b5c lw \$2,-32740\(\$3\)
# ^ local GOT entry for f_du_ic@plt
.*: .... .... jal [0-9a-f]+ <f_du_ic_dc@mips16plt>
.*: 6500 nop
.*: f030 9b40 lw \$2,-32736\(\$3\)
# ^ local GOT entry for f_du_ic_dc@plt
.*: .... .... jal [0-9a-f]+ <f_iu_dc@mips16plt>
.*: 6500 nop
.*: f070 9b4c lw \$2,-32660\(\$3\)
# ^ global GOT entry for f_iu_ic
.*: .... .... jal [0-9a-f]+ <f_iu_ic_dc@mips16plt>
.*: 6500 nop
.*: f030 9b44 lw \$2,-32732\(\$3\)
# ^ local GOT entry for f_iu_ic_dc@mips16plt
.*: .... .... jal [0-9a-f]+ <f_iu_du_dc@mips16plt>
.*: 6500 nop
.*: f030 9b48 lw \$2,-32728\(\$3\)
# ^ local GOT entry for f_iu_du_ic@plt
.*: .... .... jal [0-9a-f]+ <f_iu_du_ic_dc@mips16plt>
.*: 6500 nop
.*: f030 9b4c lw \$2,-32724\(\$3\)
# ^ local GOT entry for f_iu_du_ic_dc@plt
.*: .... .... jal [0-9a-f]+ <f_lo_dc@mips16plt>
.*: 6500 nop
.*: f030 9b50 lw \$2,-32720\(\$3\)
# ^ local GOT entry for f_lo_ic@plt
.*: .... .... jal [0-9a-f]+ <f_lo_ic_dc@mips16plt>
.*: 6500 nop
.*: f030 9b54 lw \$2,-32716\(\$3\)
# ^ local GOT entry for f_lo_ic_dc@mips16plt
.*: .... .... jal [0-9a-f]+ <f_lo_du_dc@mips16plt>
.*: 6500 nop
.*: f030 9b58 lw \$2,-32712\(\$3\)
# ^ local GOT entry for f_lo_du_ic@plt
.*: .... .... jal [0-9a-f]+ <f_lo_du_ic_dc@mips16plt>
.*: 6500 nop
.*: f030 9b5c lw \$2,-32708\(\$3\)
# ^ local GOT entry for f_lo_du_ic_dc@plt
.*: .... .... jal [0-9a-f]+ <f_lo_iu_dc@mips16plt>
.*: 6500 nop
.*: f050 9b40 lw \$2,-32704\(\$3\)
# ^ local GOT entry for f_lo_iu_ic@plt
.*: .... .... jal [0-9a-f]+ <f_lo_iu_ic_dc@mips16plt>
.*: 6500 nop
.*: f050 9b44 lw \$2,-32700\(\$3\)
# ^ local GOT entry for f_lo_iu_ic_dc@mips16plt
.*: .... .... jal [0-9a-f]+ <f_lo_iu_du_dc@mips16plt>
.*: 6500 nop
.*: f050 9b48 lw \$2,-32696\(\$3\)
# ^ local GOT entry for f_lo_iu_du_ic@plt
.*: .... .... jal [0-9a-f]+ <f_lo_iu_du_ic_dc@mips16plt>
.*: 6500 nop
.*: f050 9b4c lw \$2,-32692\(\$3\)
# ^ local GOT entry for f_lo_iu_du_ic_dc@plt
.*: e820 jr \$31
Disassembly of section \.text\.b:
10103000 <testu>:
.*: ........ jal [0-9a-f]+ <f_du@plt>
.*: 00000000 nop
.*: ........ j [0-9a-f]+ <f_du@plt>
.*: 00000000 nop
.*: ........ jal [0-9a-f]+ <f_du_dc@plt>
.*: 00000000 nop
.*: ........ j [0-9a-f]+ <f_du_dc@plt>
.*: 00000000 nop
.*: ........ jal [0-9a-f]+ <f_du_ic@plt>
.*: 00000000 nop
.*: ........ j [0-9a-f]+ <f_du_ic@plt>
.*: 00000000 nop
.*: ........ jal [0-9a-f]+ <f_du_ic_dc@plt>
.*: 00000000 nop
.*: ........ j [0-9a-f]+ <f_du_ic_dc@plt>
.*: 00000000 nop
.*: 8c628074 lw \$2,-32652\(\$3\)
# ^ global GOT entry for f_iu
.*: 8c628050 lw \$2,-32688\(\$3\)
# ^ local GOT entry for f_iu_dc@mips16plt
.*: 8c62806c lw \$2,-32660\(\$3\)
# ^ global GOT entry for f_iu_ic
.*: 8c628024 lw \$2,-32732\(\$3\)
# ^ local GOT entry for f_iu_ic_dc@mips16plt
.*: ........ jal [0-9a-f]+ <f_iu_du@plt>
.*: 00000000 nop
.*: ........ j [0-9a-f]+ <f_iu_du@plt>
.*: 00000000 nop
.*: 8c628054 lw \$2,-32684\(\$3\)
# ^ local GOT entry for f_iu_du@plt
.*: ........ jal [0-9a-f]+ <f_iu_du_dc@plt>
.*: 00000000 nop
.*: ........ j [0-9a-f]+ <f_iu_du_dc@plt>
.*: 00000000 nop
.*: 8c628058 lw \$2,-32680\(\$3\)
# ^ local GOT entry for f_iu_du_dc@plt
.*: ........ jal [0-9a-f]+ <f_iu_du_ic@plt>
.*: 00000000 nop
.*: ........ j [0-9a-f]+ <f_iu_du_ic@plt>
.*: 00000000 nop
.*: 8c628028 lw \$2,-32728\(\$3\)
# ^ local GOT entry for f_iu_du_ic@plt
.*: ........ jal [0-9a-f]+ <f_iu_du_ic_dc@plt>
.*: 00000000 nop
.*: ........ j [0-9a-f]+ <f_iu_du_ic_dc@plt>
.*: 00000000 nop
.*: 8c62802c lw \$2,-32724\(\$3\)
# ^ local GOT entry for f_iu_du_ic_dc@plt
.*: ........ jal [0-9a-f]+ <f_lo_du@plt>
.*: 00000000 nop
.*: ........ j [0-9a-f]+ <f_lo_du@plt>
.*: 00000000 nop
.*: ........ jal [0-9a-f]+ <f_lo_du_dc@plt>
.*: 00000000 nop
.*: ........ j [0-9a-f]+ <f_lo_du_dc@plt>
.*: 00000000 nop
.*: ........ jal [0-9a-f]+ <f_lo_du_ic@plt>
.*: 00000000 nop
.*: ........ j [0-9a-f]+ <f_lo_du_ic@plt>
.*: 00000000 nop
.*: ........ jal [0-9a-f]+ <f_lo_du_ic_dc@plt>
.*: 00000000 nop
.*: ........ j [0-9a-f]+ <f_lo_du_ic_dc@plt>
.*: 00000000 nop
.*: 8c62805c lw \$2,-32676\(\$3\)
# ^ local GOT entry for f_lo_iu@plt
.*: 8c628060 lw \$2,-32672\(\$3\)
# ^ local GOT entry for f_lo_iu_dc@mips16plt
.*: 8c628040 lw \$2,-32704\(\$3\)
# ^ local GOT entry for f_lo_iu_ic@plt
.*: 8c628044 lw \$2,-32700\(\$3\)
# ^ local GOT entry for f_lo_iu_ic_dc@mips16plt
.*: ........ jal [0-9a-f]+ <f_lo_iu_du@plt>
.*: 00000000 nop
.*: ........ j [0-9a-f]+ <f_lo_iu_du@plt>
.*: 00000000 nop
.*: 8c628064 lw \$2,-32668\(\$3\)
# ^ local GOT entry for f_lo_iu_du@plt
.*: ........ jal [0-9a-f]+ <f_lo_iu_du_dc@plt>
.*: 00000000 nop
.*: ........ j [0-9a-f]+ <f_lo_iu_du_dc@plt>
.*: 00000000 nop
.*: 8c628068 lw \$2,-32664\(\$3\)
# ^ local GOT entry for f_lo_iu_du_dc@plt
.*: ........ jal [0-9a-f]+ <f_lo_iu_du_ic@plt>
.*: 00000000 nop
.*: ........ j [0-9a-f]+ <f_lo_iu_du_ic@plt>
.*: 00000000 nop
.*: 8c628048 lw \$2,-32696\(\$3\)
# ^ local GOT entry for f_lo_iu_du_ic@plt
.*: ........ jal [0-9a-f]+ <f_lo_iu_du_ic_dc@plt>
.*: 00000000 nop
.*: ........ j [0-9a-f]+ <f_lo_iu_du_ic_dc@plt>
.*: 00000000 nop
.*: 8c62804c lw \$2,-32692\(\$3\)
# ^ local GOT entry for f_lo_iu_du_ic_dc@plt
.*: 03e00008 jr \$31
Disassembly of section \.text\.c:
10104000 <testlo>:
.*: 24020150 li \$2,336
# ^ low 16 bits of f_lo@plt
.*: 240201e1 li \$2,481
# ^ low 16 bits of f_lo_dc@mips16plt
.*: 24020090 li \$2,144
# ^ low 16 bits of f_lo_ic@plt
.*: 24020251 li \$2,593
# ^ low 16 bits of f_lo_ic_dc@mips16plt
.*: 24020110 li \$2,272
# ^ low 16 bits of f_lo_du@plt
.*: 240200a0 li \$2,160
# ^ low 16 bits of f_lo_du_dc@plt
.*: 24020070 li \$2,112
# ^ low 16 bits of f_lo_du_ic@plt
.*: 24020040 li \$2,64
# ^ low 16 bits of f_lo_du_ic_dc@plt
.*: 24020020 li \$2,32
# ^ low 16 bits of f_lo_iu@plt
.*: 24020191 li \$2,401
# ^ low 16 bits of f_lo_iu_dc@mips16plt
.*: 24020080 li \$2,128
# ^ low 16 bits of f_lo_iu_ic@plt
.*: 24020231 li \$2,561
# ^ low 16 bits of f_lo_iu_ic_dc@mips16plt
.*: 24020100 li \$2,256
# ^ low 16 bits of f_lo_iu_du@plt
.*: 24020030 li \$2,48
# ^ low 16 bits of f_lo_iu_du_dc@plt
.*: 24020130 li \$2,304
# ^ low 16 bits of f_lo_iu_du_ic@plt
.*: 24020140 li \$2,320
# ^ low 16 bits of f_lo_iu_du_ic_dc@plt
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