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213516ef31
This commit is the result of running the gdb/copyright.py script, which automated the update of the copyright year range for all source files managed by the GDB project to be updated to include year 2023.
82 lines
3.6 KiB
Plaintext
82 lines
3.6 KiB
Plaintext
dnl Copyright (C) 1997-2023 Free Software Foundation, Inc.
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dnl
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dnl This program is free software; you can redistribute it and/or modify
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dnl it under the terms of the GNU General Public License as published by
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dnl the Free Software Foundation; either version 3 of the License, or
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dnl (at your option) any later version.
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dnl
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dnl This program is distributed in the hope that it will be useful,
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dnl but WITHOUT ANY WARRANTY; without even the implied warranty of
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dnl MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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dnl GNU General Public License for more details.
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dnl
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dnl You should have received a copy of the GNU General Public License
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dnl along with this program. If not, see <http://www.gnu.org/licenses/>.
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dnl
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dnl --enable-sim-bitsize is for developers of the simulator
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dnl It specifies the number of BITS in the target.
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dnl arg[1] is the number of bits in a word
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dnl arg[2] is the number assigned to the most significant bit
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dnl arg[3] is the number of bits in an address
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dnl arg[4] is the number of bits in an OpenFirmware cell.
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dnl FIXME: this information should be obtained from bfd/archure
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AC_DEFUN([SIM_AC_OPTION_BITSIZE],
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wire_word_bitsize="[$1]"
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wire_word_msb="[$2]"
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wire_address_bitsize="[$3]"
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wire_cell_bitsize="[$4]"
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[AC_ARG_ENABLE(sim-bitsize,
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[AS_HELP_STRING([--enable-sim-bitsize=N], [Specify target bitsize (32 or 64)])],
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[sim_bitsize=
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case "${enableval}" in
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64,63 | 64,63,* ) sim_bitsize="-DWITH_TARGET_WORD_BITSIZE=64 -DWITH_TARGET_WORD_MSB=63";;
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32,31 | 32,31,* ) sim_bitsize="-DWITH_TARGET_WORD_BITSIZE=32 -DWITH_TARGET_WORD_MSB=31";;
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64,0 | 64,0,* ) sim_bitsize="-DWITH_TARGET_WORD_BITSIZE=32 -DWITH_TARGET_WORD_MSB=0";;
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32,0 | 64,0,* ) sim_bitsize="-DWITH_TARGET_WORD_BITSIZE=32 -DWITH_TARGET_WORD_MSB=0";;
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32) if test x"$wire_word_msb" != x -a x"$wire_word_msb" != x0; then
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sim_bitsize="-DWITH_TARGET_WORD_BITSIZE=32 -DWITH_TARGET_WORD_MSB=31"
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else
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sim_bitsize="-DWITH_TARGET_WORD_BITSIZE=32 -DWITH_TARGET_WORD_MSB=0"
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fi ;;
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64) if test x"$wire_word_msb" != x -a x"$wire_word_msb" != x0; then
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sim_bitsize="-DWITH_TARGET_WORD_BITSIZE=64 -DWITH_TARGET_WORD_MSB=63"
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else
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sim_bitsize="-DWITH_TARGET_WORD_BITSIZE=64 -DWITH_TARGET_WORD_MSB=0"
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fi ;;
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*) AC_MSG_ERROR("--enable-sim-bitsize was given $enableval. Expected 32 or 64") ;;
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esac
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# address bitsize
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tmp=`echo "${enableval}" | sed -e "s/^[[0-9]]*,*[[0-9]]*,*//"`
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case x"${tmp}" in
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x ) ;;
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x32 | x32,* ) sim_bitsize="${sim_bitsize} -DWITH_TARGET_ADDRESS_BITSIZE=32" ;;
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x64 | x64,* ) sim_bitsize="${sim_bitsize} -DWITH_TARGET_ADDRESS_BITSIZE=64" ;;
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* ) AC_MSG_ERROR("--enable-sim-bitsize was given address size $enableval. Expected 32 or 64") ;;
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esac
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# cell bitsize
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tmp=`echo "${enableval}" | sed -e "s/^[[0-9]]*,*[[0-9*]]*,*[[0-9]]*,*//"`
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case x"${tmp}" in
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x ) ;;
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x32 | x32,* ) sim_bitsize="${sim_bitsize} -DWITH_TARGET_CELL_BITSIZE=32" ;;
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x64 | x64,* ) sim_bitsize="${sim_bitsize} -DWITH_TARGET_CELL_BITSIZE=64" ;;
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* ) AC_MSG_ERROR("--enable-sim-bitsize was given cell size $enableval. Expected 32 or 64") ;;
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esac
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if test x"$silent" != x"yes" && test x"$sim_bitsize" != x""; then
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echo "Setting bitsize flags = $sim_bitsize" 6>&1
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fi],
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[sim_bitsize=""
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if test x"$wire_word_bitsize" != x; then
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sim_bitsize="$sim_bitsize -DWITH_TARGET_WORD_BITSIZE=$wire_word_bitsize"
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fi
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if test x"$wire_word_msb" != x; then
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sim_bitsize="$sim_bitsize -DWITH_TARGET_WORD_MSB=$wire_word_msb"
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fi
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if test x"$wire_address_bitsize" != x; then
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sim_bitsize="$sim_bitsize -DWITH_TARGET_ADDRESS_BITSIZE=$wire_address_bitsize"
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fi
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if test x"$wire_cell_bitsize" != x; then
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sim_bitsize="$sim_bitsize -DWITH_TARGET_CELL_BITSIZE=$wire_cell_bitsize"
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fi])dnl
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])
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AC_SUBST(sim_bitsize)
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