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280 lines
7.2 KiB
C
280 lines
7.2 KiB
C
/* Disassemble Motorola M*Core instructions.
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Copyright 1993, 1999, 2000 Free Software Foundation, Inc.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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#include "sysdep.h"
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#include <stdio.h>
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#define STATIC_TABLE
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#define DEFINE_TABLE
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#include "mcore-opc.h"
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#include "dis-asm.h"
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/* Mask for each mcore_opclass: */
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static const unsigned short imsk[] =
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{
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/* O0 */ 0xFFFF,
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/* OT */ 0xFFFC,
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/* O1 */ 0xFFF0,
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/* OC */ 0xFE00,
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/* O2 */ 0xFF00,
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/* X1 */ 0xFFF0,
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/* OI */ 0xFE00,
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/* OB */ 0xFE00,
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/* OMa */ 0xFFF0,
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/* SI */ 0xFE00,
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/* I7 */ 0xF800,
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/* LS */ 0xF000,
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/* BR */ 0xF800,
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/* BL */ 0xFF00,
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/* LR */ 0xF000,
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/* LJ */ 0xFF00,
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/* RM */ 0xFFF0,
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/* RQ */ 0xFFF0,
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/* JSR */ 0xFFF0,
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/* JMP */ 0xFFF0,
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/* OBRa*/ 0xFFF0,
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/* OBRb*/ 0xFF80,
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/* OBRc*/ 0xFF00,
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/* OBR2*/ 0xFE00,
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/* O1R1*/ 0xFFF0,
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/* OMb */ 0xFF80,
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/* OMc */ 0xFF00,
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/* SIa */ 0xFE00,
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/* MULSH */ 0xFF00,
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/* OPSR */ 0xFFF8, /* psrset/psrclr */
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/* JC */ 0, /* JC,JU,JL don't appear in object */
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/* JU */ 0,
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/* JL */ 0,
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/* RSI */ 0,
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/* DO21*/ 0,
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/* OB2 */ 0 /* OB2 won't appear in object. */
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};
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static const char * grname[] =
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{
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"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
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"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
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};
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static const char X[] = "??";
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static const char * crname[] =
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{
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"psr", "vbr", "epsr", "fpsr", "epc", "fpc", "ss0", "ss1",
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"ss2", "ss3", "ss4", "gcr", "gsr", X, X, X,
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X, X, X, X, X, X, X, X,
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X, X, X, X, X, X, X, X
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};
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static const unsigned isiz[] = { 2, 0, 1, 0 };
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int
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print_insn_mcore (memaddr, info)
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bfd_vma memaddr;
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struct disassemble_info * info;
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{
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unsigned char ibytes[4];
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fprintf_ftype fprintf = info->fprintf_func;
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void * stream = info->stream;
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unsigned short inst;
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mcore_opcode_info * op;
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int status;
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info->bytes_per_chunk = 2;
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status = info->read_memory_func (memaddr, ibytes, 2, info);
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if (status != 0)
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{
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info->memory_error_func (status, memaddr, info);
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return -1;
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}
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if (info->endian == BFD_ENDIAN_BIG)
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inst = (ibytes[0] << 8) | ibytes[1];
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else if (info->endian == BFD_ENDIAN_LITTLE)
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inst = (ibytes[1] << 8) | ibytes[0];
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else
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abort ();
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/* Just a linear search of the table. */
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for (op = mcore_table; op->name != 0; op ++)
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if (op->inst == (inst & imsk[op->opclass]))
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break;
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if (op->name == 0)
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fprintf (stream, ".short 0x%04x", inst);
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else
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{
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const char * name = grname[inst & 0x0F];
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fprintf (stream, "%s", op->name);
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switch (op->opclass)
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{
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case O0: break;
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case OT: fprintf (stream, "\t%d", inst & 0x3); break;
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case O1:
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case JMP:
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case JSR: fprintf (stream, "\t%s", name); break;
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case OC: fprintf (stream, "\t%s, %s", name, crname[(inst >> 4) & 0x1F]); break;
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case O1R1: fprintf (stream, "\t%s, r1", name); break;
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case MULSH:
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case O2: fprintf (stream, "\t%s, %s", name, grname[(inst >> 4) & 0xF]); break;
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case X1: fprintf (stream, "\tr1, %s", name); break;
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case OI: fprintf (stream, "\t%s, %d", name, ((inst >> 4) & 0x1F) + 1); break;
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case RM: fprintf (stream, "\t%s-r15, (r0)", name); break;
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case RQ: fprintf (stream, "\tr4-r7, (%s)", name); break;
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case OB:
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case OBRa:
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case OBRb:
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case OBRc:
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case SI:
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case SIa:
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case OMa:
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case OMb:
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case OMc: fprintf (stream, "\t%s, %d", name, (inst >> 4) & 0x1F); break;
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case I7: fprintf (stream, "\t%s, %d", name, (inst >> 4) & 0x7F); break;
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case LS: fprintf (stream, "\t%s, (%s, %d)", grname[(inst >> 8) & 0xF],
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name, ((inst >> 4) & 0xF) << isiz[(inst >> 13) & 3]);
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break;
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case BR:
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{
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long val = inst & 0x3FF;
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if (inst & 0x400)
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val |= 0xFFFFFC00;
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fprintf (stream, "\t0x%x", memaddr + 2 + (val<<1));
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if (strcmp (op->name, "bsr") == 0)
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{
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/* For bsr, we'll try to get a symbol for the target. */
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val = memaddr + 2 + (val << 1);
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if (info->print_address_func && val != 0)
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{
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fprintf (stream, "\t// ");
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info->print_address_func (val, info);
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}
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}
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}
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break;
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case BL:
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{
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long val;
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val = (inst & 0x000F);
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fprintf (stream, "\t%s, 0x%x",
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grname[(inst >> 4) & 0xF], memaddr - (val << 1));
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}
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break;
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case LR:
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{
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unsigned long val;
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val = (memaddr + 2 + ((inst & 0xFF) << 2)) & 0xFFFFFFFC;
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status = info->read_memory_func (val, ibytes, 4, info);
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if (status != 0)
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{
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info->memory_error_func (status, memaddr, info);
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break;
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}
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if (info->endian == BFD_ENDIAN_LITTLE)
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val = (ibytes[3] << 24) | (ibytes[2] << 16)
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| (ibytes[1] << 8) | (ibytes[0]);
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else
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val = (ibytes[0] << 24) | (ibytes[1] << 16)
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| (ibytes[2] << 8) | (ibytes[3]);
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/* Removed [] around literal value to match ABI syntax 12/95. */
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fprintf (stream, "\t%s, 0x%X", grname[(inst >> 8) & 0xF], val);
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if (val == 0)
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fprintf (stream, "\t// from address pool at 0x%x",
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(memaddr + 2 + ((inst & 0xFF) << 2)) & 0xFFFFFFFC);
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}
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break;
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case LJ:
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{
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unsigned long val;
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val = (memaddr + 2 + ((inst & 0xFF) << 2)) & 0xFFFFFFFC;
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status = info->read_memory_func (val, ibytes, 4, info);
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if (status != 0)
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{
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info->memory_error_func (status, memaddr, info);
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break;
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}
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if (info->endian == BFD_ENDIAN_LITTLE)
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val = (ibytes[3] << 24) | (ibytes[2] << 16)
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| (ibytes[1] << 8) | (ibytes[0]);
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else
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val = (ibytes[0] << 24) | (ibytes[1] << 16)
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| (ibytes[2] << 8) | (ibytes[3]);
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/* Removed [] around literal value to match ABI syntax 12/95. */
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fprintf (stream, "\t0x%X", val);
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/* For jmpi/jsri, we'll try to get a symbol for the target. */
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if (info->print_address_func && val != 0)
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{
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fprintf (stream, "\t// ");
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info->print_address_func (val, info);
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}
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else
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{
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fprintf (stream, "\t// from address pool at 0x%x",
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(memaddr + 2 + ((inst & 0xFF) << 2)) & 0xFFFFFFFC);
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}
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}
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break;
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case OPSR:
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{
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static char * fields[] =
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{
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"af", "ie", "fe", "fe,ie",
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"ee", "ee,ie", "ee,fe", "ee,fe,ie"
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};
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fprintf (stream, "\t%s", fields[inst & 0x7]);
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}
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break;
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default:
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/* If the disassembler lags the instruction set. */
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fprintf (stream, "\tundecoded operands, inst is 0x%04x", inst);
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break;
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}
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}
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/* Say how many bytes we consumed. */
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return 2;
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}
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