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bd30e45a34
* configure: Add microblaze-*.* (not regenerated).
* configure.ac: Likewise.
* microblaze/config.in: New.
* microblaze/configure: Generate.
* microblaze/configure.ac: New.
* microblaze/interp.c: New.
* microblaze/Makefile.in: New.
* microblaze/microblaze.h: New.
* microblaze/microblaze.isa: New.
* microblaze/sim-main.h: New.
* microblaze/sysdep.h: New.
107 lines
3.0 KiB
C
107 lines
3.0 KiB
C
#ifndef MICROBLAZE_H
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#define MICROBLAZE_H
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/* Copyright 2009 Free Software Foundation, Inc.
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This file is part of the Xilinx MicroBlaze simulator.
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This library is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
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MA 02110-1301, USA. */
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#include "../../opcodes/microblaze-opcm.h"
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#define GET_RD ((inst & RD_MASK) >> RD_LOW)
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#define GET_RA ((inst & RA_MASK) >> RA_LOW)
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#define GET_RB ((inst & RB_MASK) >> RB_LOW)
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#define CPU microblaze_state.cpu[0].microblaze_cpu
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#define RD CPU.regs[rd]
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#define RA CPU.regs[ra]
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#define RB CPU.regs[rb]
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/* #define IMM immword */
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#define SA CPU.spregs[IMM & 0x1]
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#define IMM_H CPU.imm_high
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#define IMM_L ((inst & IMM_MASK) >> IMM_LOW)
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#define IMM_ENABLE CPU.imm_enable
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#define IMM (IMM_ENABLE ? \
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(((uhalf)IMM_H << 16) | (uhalf)IMM_L) : \
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(imm_unsigned ? \
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(0xFFFF & IMM_L) : \
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(IMM_L & 0x8000 ? \
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(0xFFFF0000 | IMM_L) : \
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(0x0000FFFF & IMM_L))))
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#define PC CPU.spregs[0]
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#define MSR CPU.spregs[1]
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#define SP CPU.regs[29]
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#define RETREG CPU.regs[3]
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#define MEM(X) memory[X]
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#define MEM_RD_BYTE(X) rbat(X)
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#define MEM_RD_HALF(X) rhat(X)
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#define MEM_RD_WORD(X) rlat(X)
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#define MEM_RD_UBYTE(X) (ubyte) MEM_RD_BYTE(X)
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#define MEM_RD_UHALF(X) (uhalf) MEM_RD_HALF(X)
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#define MEM_RD_UWORD(X) (uword) MEM_RD_WORD(X)
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#define MEM_WR_BYTE(X, D) wbat(X, D)
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#define MEM_WR_HALF(X, D) what(X, D)
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#define MEM_WR_WORD(X, D) wlat(X, D)
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#define MICROBLAZE_SEXT8(X) ((char) X)
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#define MICROBLAZE_SEXT16(X) ((short) X)
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#define CARRY carry
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#define C_rd ((MSR & 0x4) >> 2)
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#define C_wr(D) MSR = (D ? MSR | 0x80000004 : MSR & 0x7FFFFFFB)
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#define C_calc(X, Y, C) ((((uword)Y == MAX_WORD) && (C == 1)) ? \
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1 : \
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((MAX_WORD - (uword)X) < ((uword)Y + C)))
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#define BIP_MASK 0x00000008
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#define CARRY_MASK 0x00000004
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#define INTR_EN_MASK 0x00000002
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#define BUSLOCK_MASK 0x00000001
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#define DELAY_SLOT delay_slot_enable = 1
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#define BRANCH branch_taken = 1
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#define NUM_REGS 32
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#define NUM_SPECIAL 2
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#define INST_SIZE 4
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#define MAX_WORD 0xFFFFFFFF
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#define MICROBLAZE_HALT_INST 0xb8000000
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typedef char byte;
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typedef short half;
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typedef int word;
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typedef unsigned char ubyte;
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typedef unsigned short uhalf;
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typedef unsigned int uword;
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#endif /* MICROBLAZE_H */
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