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According to the riscv privilege spec, some CSR are only valid when rv32 or the specific extension is set. We extend the DECLARE_CSR and DECLARE_CSR_ALIAS to record more informaton we need, and then check whether the CSR is valid according to these information. We report warning message when the CSR is invalid, so we have a choice between error and warning by --fatal-warnings option. Also, a --no-warn/-W option is used to turn the warnings off, if people don't want the warnings. gas/ * config/tc-riscv.c (enum riscv_csr_class): New enum. Used to decide whether or not this CSR is legal in the current ISA string. (struct riscv_csr_extra): New structure to hold all extra information of CSR. (riscv_init_csr_hash): New function. According to the DECLARE_CSR and DECLARE_CSR_ALIAS, insert CSR extra information into csr_extra_hash. Call hash_reg_name to insert CSR address into reg_names_hash. (md_begin): Call riscv_init_csr_hashes for each DECLARE_CSR. (reg_csr_lookup_internal, riscv_csr_class_check): New functions. Decide whether the CSR is valid according to the csr_extra_hash. (init_opcode_hash): Update 'if (hash_error != NULL)' as hash_error is not a boolean. This is same as riscv_init_csr_hash, so keep the consistent usage. * testsuite/gas/riscv/csr-dw-regnums.d: Add -march=rv32if option. * testsuite/gas/riscv/priv-reg.d: Add f-ext by -march option. * testsuite/gas/riscv/priv-reg-fail-fext.d: New testcase. The source file is `priv-reg.s`, and the ISA is rv32i without f-ext, so the f-ext CSR are not allowed. * testsuite/gas/riscv/priv-reg-fail-fext.l: Likewise. * testsuite/gas/riscv/priv-reg-fail-rv32-only.d: New testcase. The source file is `priv-reg.s`, and the ISA is rv64if, so the rv32-only CSR are not allowed. * testsuite/gas/riscv/priv-reg-fail-rv32-only.l: Likewise. include/ * opcode/riscv-opc.h: Extend DECLARE_CSR and DECLARE_CSR_ALIAS to record riscv_csr_class. opcodes/ * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is changed. gdb/ * riscv-tdep.c: Updated since the DECLARE_CSR is changed. * riscv-tdep.h: Likewise. * features/riscv/rebuild-csr-xml.sh: Generate the 64bit-csr.xml without rv32-only CSR. * features/riscv/64bit-csr.xml: Regernated. binutils/ * dwarf.c: Updated since the DECLARE_CSR is changed.
139 lines
3.9 KiB
Plaintext
139 lines
3.9 KiB
Plaintext
2020-02-20 Nelson Chu <nelson.chu@sifive.com>
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* opcode/riscv-opc.h: Extend DECLARE_CSR and DECLARE_CSR_ALIAS to
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record riscv_csr_class.
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2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
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Matthew Malcomson <matthew.malcomson@arm.com>
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* opcode/arm.h (ARM_EXT2_CDE): New extension macro.
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(ARM_EXT2_CDE0): New extension macro.
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(ARM_EXT2_CDE1): New extension macro.
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(ARM_EXT2_CDE2): New extension macro.
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(ARM_EXT2_CDE3): New extension macro.
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(ARM_EXT2_CDE4): New extension macro.
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(ARM_EXT2_CDE5): New extension macro.
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(ARM_EXT2_CDE6): New extension macro.
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(ARM_EXT2_CDE7): New extension macro.
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2020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
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PR 25469
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* coff/internal.h (R_IMM16BE): Define.
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* elf/z80.h (EF_Z80_MACH_Z80N): Define.
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(R_Z80_16_BE): New reloc.
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2020-02-04 Alan Modra <amodra@gmail.com>
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* opcode/d30v.h (struct pd_reg): Make value field unsigned.
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2020-01-16 Jon Turney <jon.turney@dronecode.org.uk>
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* coff/internal.h (PE_IMAGE_DEBUG_TYPE_VC_FEATURE)
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(PE_IMAGE_DEBUG_TYPE_POGO, PE_IMAGE_DEBUG_TYPE_ILTCG)
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(PE_IMAGE_DEBUG_TYPE_MPX, PE_IMAGE_DEBUG_TYPE_REPRO): Add.
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2020-01-18 Nick Clifton <nickc@redhat.com>
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Binutils 2.34 branch created.
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2020-01-17 Nick Clifton <nickc@redhat.com>
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* Import from gcc mainline:
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2019-06-10 Martin Liska <mliska@suse.cz>
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* ansidecl.h (ATTRIBUTE_WARN_UNUSED_RESULT): New macro.
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* libiberty.h (xmalloc): Use it.
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(xrealloc): Likewise.
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(xcalloc): Likewise.
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(xstrdup): Likewise.
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(xstrndup): Likewise.
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(xmemdup): Likewise.
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2019-06-10 Martin Liska <mliska@suse.cz>
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* ansidecl.h:
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(ATTRIBUTE_RESULT_SIZE_1): Define new macro.
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(ATTRIBUTE_RESULT_SIZE_2): Likewise.
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(ATTRIBUTE_RESULT_SIZE_1_2): Likewise.
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* libiberty.h (xmalloc): Add RESULT_SIZE attribute.
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(xrealloc): Likewise.
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(xcalloc): Likewise.
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2019-11-16 Tim Ruehsen <tim.ruehsen@gmx.de>
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* demangle.h (struct demangle_component): Add member
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d_counting.
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2019-11-16 Eduard-Mihai Burtescu <eddyb@lyken.rs>
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* demangle.h (rust_demangle_callback): Add.
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2019-07-18 Eduard-Mihai Burtescu <eddyb@lyken.rs>
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* demangle.h (rust_is_mangled): Move to libiberty/rust-demangle.h.
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(rust_demangle_sym): Move to libiberty/rust-demangle.h.
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2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
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PR 25376
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* opcodes/arm.h (FPU_MVE, FPU_MVE_FPU): Move these features to...
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(ARM_EXT2_MVE, ARM_EXT2_MVE_FP): ... the CORE_HIGH space.
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(ARM_ANY): Redefine to not include any MVE bits.
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(ARM_FEATURE_ALL): Removed.
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2020-01-15 Jozef Lawrynowicz <jozef.l@mittosystems.com>
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* opcode/msp430.h (enum msp430_expp_e): New.
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(struct msp430_operand_s): Add expp member to struct.
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2020-01-13 Claudiu Zissulescu <claziss@gmail.com>
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* elf/arc-cpu.def: Update ARC cpu list.
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2020-01-13 Alan Modra <amodra@gmail.com>
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* opcode/tic4x.h (EXTR): Delete.
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(EXTRU, EXTRS, INSERTU, INSERTS): Rewrite without zero/sign
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extension using shifts. Do trim INSERTU value to specified bitfield.
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2020-01-10 Alan Modra <amodra@gmail.com>
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* opcode/spu.h: Formatting.
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(UNSIGNED_EXTRACT): Use 1u.
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(SIGNED_EXTRACT): Don't sign extend with shifts.
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(DECODE_INSN_I9a, DECODE_INSN_I9b): Avoid left shift of signed value.
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Keep result signed.
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(DECODE_INSN_U9a, DECODE_INSN_U9b): Delete.
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2020-01-07 Shahab Vahedi <shahab@synopsys.com>
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* opcode/arc.h (insn_class_t): Add 'LLOCK' and 'SCOND'.
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2020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
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* coff/internal.h: Add defintions of Z80 reloc names.
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2020-01-02 Christian Biesinger <cbiesinger@google.com>
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* opcode/s12z.h: Undef REG_Y.
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2020-01-01 Alan Modra <amodra@gmail.com>
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Update year range in copyright notice of all files.
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For older changes see ChangeLog-2019
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Copyright (C) 2020 Free Software Foundation, Inc.
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Copying and distribution of this file, with or without modification,
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are permitted in any medium without royalty provided the copyright
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notice and this notice are preserved.
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Local Variables:
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mode: change-log
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left-margin: 8
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fill-column: 74
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version-control: never
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End:
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