binutils-gdb/binutils/testsuite/binutils-all/aarch64/in-order-all.d
Alex Coplan 09c1e68a16 AArch64: add GAS support for UDF instruction
binutils * testsuite/binutils-all/aarch64/in-order-all.d: Update to use new
          disassembly.
        * testsuite/binutils-all/aarch64/out-of-order-all.d: Likewise.

ld/     * testsuite/ld-aarch64/erratum843419_tls_ie.d: Use udf in disassembly.
        * testsuite/ld-aarch64/farcall-b-section.d: Likewise.
        * testsuite/ld-aarch64/farcall-back.d: Likewise.
        * testsuite/ld-aarch64/farcall-bl-section.d: Likewise.

gas/   * config/tc-aarch64.c (fix_insn): Implement for AARCH64_OPND_UNDEFINED.
          (parse_operands): Implement for AARCH64_OPND_UNDEFINED.
        * testsuite/gas/aarch64/udf.s: New.
        * testsuite/gas/aarch64/udf.d: New.
        * testsuite/gas/aarch64/udf-invalid.s: New.
        * testsuite/gas/aarch64/udf-invalid.l: New.
        * testsuite/gas/aarch64/udf-invalid.d: New.

include * opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_UNDEFINED.

opcodes * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
        * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
          (operand_general_constraint_met_p): validate AARCH64_OPND_UNDEFINED.
        * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry for
          FLD_imm16_2.
        * aarch64-asm-2.c: Regenerated.
        * aarch64-dis-2.c: Regenerated.
        * aarch64-opc-2.c: Regenerated.
2020-04-30 15:47:30 +01:00

39 lines
720 B
Makefile

#PROG: objcopy
#source: out-of-order.s
#ld: -e v1 -Ttext-segment=0x400000
#objdump: -D
#name: Check if disassembler can handle all sections in default order
.*: +file format .*aarch64.*
Disassembly of section \.func1:
.+ <v1>:
[^:]+: 8b010000 add x0, x0, x1
[^:]+: 00000000 udf #0
Disassembly of section \.func2:
.+ <\.func2>:
[^:]+: 8b010000 add x0, x0, x1
Disassembly of section \.func3:
.+ <\.func3>:
[^:]+: 8b010000 add x0, x0, x1
[^:]+: 8b010000 add x0, x0, x1
[^:]+: 8b010000 add x0, x0, x1
[^:]+: 8b010000 add x0, x0, x1
[^:]+: 8b010000 add x0, x0, x1
[^:]+: 00000000 udf #0
Disassembly of section \.rodata:
.+ <\.rodata>:
[^:]+: 00000000 udf #0
Disassembly of section .global:
.+ <.+>:
...