mirror of
https://sourceware.org/git/binutils-gdb.git
synced 2025-01-12 12:16:04 +08:00
06c441ccef
2022-02-01 Ali Lown <ali.lown@imgtec.com> Andrew Bennett <andrew.bennett@imgtec.com> Dragan Mladjenovic <dragan.mladjenovic@rt-rk.com> Faraz Shahbazker <fshahbazker@wavecomp.com> sim/common/ChangeLog: * sim-bits.h (EXTEND9, EXTEND18 ,EXTEND19, EXTEND21, EXTEND26): New macros. sim/mips/ChangeLog: * Makefile.in (IGEN_INCLUDE): Add mips3264r6.igen. * configure: Regenerate. * configure.ac: Support mipsisa32r6 and mipsisa64r6. (sim_engine_run): Pick simulator model from processor specified in e_flags. * cp1.c (value_fpr): Handle fmt_dc32. (fp_unary, fp_binary): Zero initialize locals. (update_fcsr, fp_classify, fp_rint, fp_r6_cmp, inner_fmac, fp_fmac, fp_min, fp_max, fp_mina, fp_maxa, fp_fmadd, fp_fmsub): New functions. (sim_fpu_class_mips_mapping): New. * cp1.h (fcsr_ABS2008_mask, fcsr_ABS2008_shift): New define. * interp.c (MIPSR6_P): New. (load_word): Allow unaligned memory access for MIPSR6. * micromips.igen (sc, scd): Adapt to new do_sc* helper signature. * mips.igen: Add *r6 models. (signal_if_cti, forbiddenslot32): New helpers. (delayslot32): Use signal_if_cti. (do_sc, do_scd); Add store_ll_bit parameter. (sc, scd): Adapt to previous change. (nal, beq, bal): New definitions for *r6. (sll): Split nop and ssnop cases into ... (nop, ssnop): New definitions. (loadstore_ea): Use the 32-bit compatibility adressing. (cache): Split logic into ... (do_cache): New helper. (check_fpu): Select IEEE 754-2008 mode for R6. (not_word_value, unpredictable, check_mt_hilo, check_mf_hilo, check_multi_hilo, check_div_hilo, check_u64, do_dmfc1b, add, li, addu, and, andi, bgez, bgtz, blez, bltz, bne, break, dadd, daddiu, daddu, dror, dror32, drorv, dsll, dsll32, dsllv, dsra, dsra32, dsrav, dsrl, dsrl32, dsub, dsubu, j, jal, jalr, jalr.hb, lb, lbu, ld, lh, lhu, lui, lw, lwu, nor, or, ori, ror, rorv, sb, sd, sh, sll, sllv, slt, slti, sltiu, sltu, sra, srav, srl, srlv, sub, subu, sw, sync, syscall, teq, tge, tgeu, tlt, tltu, tne, xor, xori, check_fmt_p, do_load_double, do_store_double, abs.FMT, add.FMT, ceil.l.FMT, ceil.w.FMT, cfc1, ctc1, cvt.d.FMT, cvt.l.FMT, cvt.w.FMT, div.FMT, dfmc1, dmtc1, floor.l.FMT, floor.w.FMT, ldc1, lwc1, mfc1, mov.FMT, mtc1, mul.FMT, recip.FMT, round.l.FMT, round.w.FMT, rsqrt.FMT, sdc1, sqrt.FMT, sub.FMT, swc1, trunc.l.FMT, trunc.w.FMT, bc0f, bc0fl, bc0t, bc0tl, dmfc0, dmtc0, eret, mfc0, mtc0, cop, tlbp, tlbr, tlbwi, tlbwr): Enable on *r6 models. * mips3264r2.igen (dext, dextm, dextu, di, dins, dinsm, dinsu, dsbh, dshd, ei, ext, mfhc1, mthc1, ins, seb, seh, synci, rdhwr, wsbh): Likewise. * mips3264r6.igen: New file. * sim-main.h (FP_formats): Add fmt_dc32. (FORBIDDEN_SLOT): New macros. (simFORBIDDENSLOT, FP_R6CMP_*, FP_R6CLASS_*): New defines. (fp_r6_cmp, fp_classify, fp_rint, fp_min, fp_max, fp_mina, fp_maxa, fp_fmadd, fp_fmsub): New declarations. (R6Compare, Classify, RoundToIntegralExact, Min, Max, MinA, MaxA, FusedMultiplyAdd, FusedMultiplySub): New macros. Wrapping previous declarations. sim/testsuite/mips/ChangeLog: * basic.exp: Add r6-*.s tests. (run_r6_removed_test): New function. (run_endian_tests): New function. * hilo-hazard-3.s: Skip for mips*r6. * r2-fpu.s: New test. * r6-64.s: New test. * r6-branch.s: New test. * r6-forbidden.s: New test. * r6-fpu.s: New test. * r6-llsc-dp.s: New test. * r6-llsc-wp.s: New test. * r6-removed.csv: New test. * r6-removed.s: New test. * r6.s: New test. * utils-r6.inc: New inc.
164 lines
3.6 KiB
ArmAsm
164 lines
3.6 KiB
ArmAsm
# mips r6 tests (non FPU)
|
|
# mach: mips32r6 mips64r6
|
|
# as: -mabi=eabi
|
|
# ld: -N -Ttext=0x80010000
|
|
# output: *\\npass\\n
|
|
|
|
.include "testutils.inc"
|
|
.include "utils-r6.inc"
|
|
|
|
setup
|
|
|
|
.data
|
|
dval1: .word 0xabcd1234
|
|
dval2: .word 0x1234eeff
|
|
.fill 248,1,0
|
|
dval3: .word 0x55555555
|
|
.fill 260,1,0
|
|
dval4: .word 0xaaaaaaaa
|
|
.text
|
|
|
|
.set noreorder
|
|
|
|
.ent DIAG
|
|
DIAG:
|
|
|
|
writemsg "[1] Test MUL"
|
|
r6ck_2r mul, 7, 9, 63
|
|
r6ck_2r mul, -7, -9, 63
|
|
r6ck_2r mul, 61, -11, -671
|
|
r6ck_2r mul, 1001, 1234, 1235234
|
|
r6ck_2r mul, 123456789, 999999, 0x7eb1e22b
|
|
r6ck_2r mul, 0xaaaabbbb, 0xccccdddd, 0x56787f6f
|
|
|
|
writemsg "[2] Test MUH"
|
|
r6ck_2r muh, 61, -11, 0xffffffff
|
|
r6ck_2r muh, 1001, 1234, 0
|
|
r6ck_2r muh, 123456789, 999999, 0x7048
|
|
r6ck_2r muh, 0xaaaabbbb, 0xccccdddd, 0x111107f7
|
|
|
|
writemsg "[3] Test MULU"
|
|
r6ck_2r mulu, 7, 9, 63
|
|
r6ck_2r mulu, -7, -9, 63
|
|
r6ck_2r mulu, 61, -11, -671
|
|
r6ck_2r mulu, 1001, 1234, 1235234
|
|
r6ck_2r mulu, 123456789, 999999, 0x7eb1e22b
|
|
r6ck_2r mulu, 0xaaaabbbb, 0xccccdddd, 0x56787f6f
|
|
|
|
writemsg "[4] Test MUHU"
|
|
r6ck_2r muhu, 1001, 1234, 0
|
|
r6ck_2r muhu, 123456789, 999999, 0x7048
|
|
r6ck_2r muhu, 0xaaaabbbb, 0xccccdddd, 0x8888a18f
|
|
r6ck_2r muhu, 0xaaaabbbb, 0xccccdddd, 0x8888a18f
|
|
|
|
writemsg "[5] Test DIV"
|
|
r6ck_2r div, 10001, 10, 1000
|
|
r6ck_2r div, -123456, 560, -220
|
|
r6ck_2r div, 9, 100, 0
|
|
|
|
writemsg "[6] Test MOD"
|
|
r6ck_2r mod, 10001, 10, 1
|
|
r6ck_2r mod, -123456, 560, 0xffffff00
|
|
r6ck_2r mod, 9, 100, 9
|
|
|
|
writemsg "[7] Test DIVU"
|
|
r6ck_2r divu, 10001, 10, 1000
|
|
r6ck_2r divu, -123456, 560, 0x750674
|
|
r6ck_2r divu, 9, 100, 0
|
|
r6ck_2r divu, 0xaaaabbbb, 3, 0x38e393e9
|
|
|
|
writemsg "[8] Test MODU"
|
|
r6ck_2r modu, 10001, 10, 1
|
|
r6ck_2r modu, -123456, 560, 0
|
|
r6ck_2r modu, 9, 100, 9
|
|
r6ck_2r modu, 0xaaaabbbb, 5, 4
|
|
|
|
writemsg "[9] Test LSA"
|
|
r6ck_2r1i lsa, 1, 2, 2, 6
|
|
r6ck_2r1i lsa, 0x8000, 0xa000, 1, 0x1a000
|
|
r6ck_2r1i lsa, 0x82, 0x2000068, 4, 0x2000888
|
|
|
|
writemsg "[10] Test AUI"
|
|
r6ck_1r1i aui, 0x0000c0de, 0xdead, 0xdeadc0de
|
|
r6ck_1r1i aui, 0x00005678, 0x1234, 0x12345678
|
|
r6ck_1r1i aui, 0x0000eeff, 0xabab, 0xababeeff
|
|
|
|
writemsg "[11] Test SELEQZ"
|
|
r6ck_2r seleqz, 0x1234, 0, 0x1234
|
|
r6ck_2r seleqz, 0x1234, 4, 0
|
|
r6ck_2r seleqz, 0x80010001, 0, 0x80010001
|
|
|
|
writemsg "[12] Test SELNEZ"
|
|
r6ck_2r selnez, 0x1234, 0, 0
|
|
r6ck_2r selnez, 0x1234, 1, 0x1234
|
|
r6ck_2r selnez, 0x80010001, 0xffffffff, 0x80010001
|
|
|
|
writemsg "[13] Test ALIGN"
|
|
r6ck_2r1i align, 0xaabbccdd, 0xeeff0011, 1, 0xff0011aa
|
|
r6ck_2r1i align, 0xaabbccdd, 0xeeff0011, 3, 0x11aabbcc
|
|
|
|
writemsg "[14] Test BITSWAP"
|
|
r6ck_1r bitswap, 0xaabbccdd, 0x55dd33bb
|
|
r6ck_1r bitswap, 0x11884422, 0x88112244
|
|
|
|
writemsg "[15] Test CLZ"
|
|
r6ck_1r clz, 0x00012340, 15
|
|
r6ck_1r clz, 0x80012340, 0
|
|
r6ck_1r clz, 0x40012340, 1
|
|
|
|
writemsg "[16] Test CLO"
|
|
r6ck_1r clo, 0x00123050, 0
|
|
r6ck_1r clo, 0xff123050, 8
|
|
r6ck_1r clo, 0x8f123050, 1
|
|
|
|
writemsg "[17] Test ADDIUPC"
|
|
jal GetPC
|
|
nop
|
|
addiu $4, $6, 8
|
|
addiupc $5, 4
|
|
fp_assert $4, $5
|
|
|
|
writemsg "[18] Test AUIPC"
|
|
jal GetPC
|
|
nop
|
|
addiu $4, $6, 8
|
|
aui $4, $4, 8
|
|
auipc $5, 8
|
|
fp_assert $4, $5
|
|
|
|
writemsg "[19] Test ALUIPC"
|
|
jal GetPC
|
|
nop
|
|
addiu $4, $6, 16
|
|
aui $4, $4, 8
|
|
li $7, 0xffff0000
|
|
and $4, $4, $7
|
|
aluipc $5, 8
|
|
fp_assert $4, $5
|
|
|
|
writemsg "[20] Test LWPC"
|
|
lw $5, dval1
|
|
lwpc $4, dval1
|
|
fp_assert $4, $5
|
|
lw $5, dval2
|
|
lwpc $4, dval2
|
|
fp_assert $4, $5
|
|
|
|
writemsg "[21] Test LL"
|
|
lw $5, dval2
|
|
la $3, dval3
|
|
ll $4, -252($3)
|
|
fp_assert $4, $5
|
|
|
|
writemsg "[22] Test SC"
|
|
ll $4, -252($3)
|
|
li $4, 0xafaf
|
|
sc $4, -252($3)
|
|
lw $5, dval2
|
|
li $4, 0xafaf
|
|
fp_assert $4, $5
|
|
|
|
pass
|
|
|
|
.end DIAG
|