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3c4c0a18c8
Adjust x86-64 linker tests after reverting
commit 31b4d3a16f
Author: Alan Modra <amodra@gmail.com>
Date: Thu Feb 3 08:57:47 2022 +1030
PR28824, relro security issues, x86 keep COMMONPAGESIZE relro
to use MAXPAGESIZE for the end of the relro segment alignment, like other
ELF targets.
* testsuite/ld-x86-64/plt-main-bnd.dd: Updated.
* testsuite/ld-x86-64/plt-main-ibt-x32.dd: Likewise.
* testsuite/ld-x86-64/plt-main-ibt.dd: Likewise.
* testsuite/ld-x86-64/pr14207.d: Likewise.
* testsuite/ld-x86-64/pr18176.d: Likewise.
* testsuite/ld-x86-64/pr20830a-now.d: Likewise.
* testsuite/ld-x86-64/pr20830a.d: Likewise.
* testsuite/ld-x86-64/pr20830b-now.d: Likewise.
* testsuite/ld-x86-64/pr20830b.d: Likewise.
* testsuite/ld-x86-64/pr21038a-now.d: Likewise.
* testsuite/ld-x86-64/pr21038a.d: Likewise.
* testsuite/ld-x86-64/pr21038b-now.d: Likewise.
* testsuite/ld-x86-64/pr21038b.d: Likewise.
* testsuite/ld-x86-64/pr21038c-now.d: Likewise.
* testsuite/ld-x86-64/pr21038c.d: Likewise.
88 lines
2.6 KiB
Makefile
88 lines
2.6 KiB
Makefile
#name: PR ld/21038 (.plt.got and .plt.sec, -z now)
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#source: pr21038c.s
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#as: --64
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#ld: -z now -z bndplt -melf_x86_64 -shared -z relro --ld-generated-unwind-info --hash-style=sysv -z max-page-size=0x200000 -z noseparate-code $NO_DT_RELR_LDFLAGS
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#objdump: -dw -Wf
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.*: +file format .*
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Contents of the .eh_frame section:
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0+ 0000000000000014 00000000 CIE
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Version: 1
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Augmentation: "zR"
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Code alignment factor: 1
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Data alignment factor: -8
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Return address column: 16
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Augmentation data: 1b
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DW_CFA_def_cfa: r7 \(rsp\) ofs 8
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DW_CFA_offset: r16 \(rip\) at cfa-8
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DW_CFA_nop
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DW_CFA_nop
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0+18 0000000000000014 0000001c FDE cie=00000000 pc=0000000000000220..0000000000000231
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DW_CFA_nop
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DW_CFA_nop
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DW_CFA_nop
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DW_CFA_nop
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DW_CFA_nop
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DW_CFA_nop
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DW_CFA_nop
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0+30 0000000000000024 00000034 FDE cie=00000000 pc=00000000000001f0..0000000000000210
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DW_CFA_def_cfa_offset: 16
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DW_CFA_advance_loc: 6 to 00000000000001f6
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DW_CFA_def_cfa_offset: 24
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DW_CFA_advance_loc: 10 to 0000000000000200
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DW_CFA_def_cfa_expression \(DW_OP_breg7 \(rsp\): 8; DW_OP_breg16 \(rip\): 0; DW_OP_lit15; DW_OP_and; DW_OP_lit5; DW_OP_ge; DW_OP_lit3; DW_OP_shl; DW_OP_plus\)
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DW_CFA_nop
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DW_CFA_nop
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DW_CFA_nop
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DW_CFA_nop
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0+58 0000000000000014 0000005c FDE cie=00000000 pc=0000000000000210..0000000000000218
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DW_CFA_nop
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DW_CFA_nop
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DW_CFA_nop
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DW_CFA_nop
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DW_CFA_nop
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DW_CFA_nop
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DW_CFA_nop
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0+70 0000000000000010 00000074 FDE cie=00000000 pc=0000000000000218..0000000000000220
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DW_CFA_nop
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DW_CFA_nop
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DW_CFA_nop
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Disassembly of section .plt:
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0+1f0 <.plt>:
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+[a-f0-9]+: ff 35 ea fd 3f 00 push 0x3ffdea\(%rip\) # 3fffe0 <_GLOBAL_OFFSET_TABLE_\+0x8>
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+[a-f0-9]+: f2 ff 25 eb fd 3f 00 bnd jmp \*0x3ffdeb\(%rip\) # 3fffe8 <_GLOBAL_OFFSET_TABLE_\+0x10>
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+[a-f0-9]+: 0f 1f 00 nopl \(%rax\)
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+[a-f0-9]+: 68 00 00 00 00 push \$0x0
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+[a-f0-9]+: f2 e9 e5 ff ff ff bnd jmp 1f0 <func1@plt-0x20>
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+[a-f0-9]+: 0f 1f 44 00 00 nopl 0x0\(%rax,%rax,1\)
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Disassembly of section .plt.got:
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0+210 <func1@plt>:
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+[a-f0-9]+: f2 ff 25 e1 fd 3f 00 bnd jmp \*0x3ffde1\(%rip\) # 3ffff8 <func1>
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+[a-f0-9]+: 90 nop
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Disassembly of section .plt.sec:
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0+218 <func2@plt>:
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+[a-f0-9]+: f2 ff 25 d1 fd 3f 00 bnd jmp \*0x3ffdd1\(%rip\) # 3ffff0 <func2>
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+[a-f0-9]+: 90 nop
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Disassembly of section .text:
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0+220 <foo>:
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+[a-f0-9]+: e8 eb ff ff ff call 210 <func1@plt>
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+[a-f0-9]+: e8 ee ff ff ff call 218 <func2@plt>
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+[a-f0-9]+: 48 8b 05 c7 fd 3f 00 mov 0x3ffdc7\(%rip\),%rax # 3ffff8 <func1>
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#pass
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