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3c4c0a18c8
Adjust x86-64 linker tests after reverting
commit 31b4d3a16f
Author: Alan Modra <amodra@gmail.com>
Date: Thu Feb 3 08:57:47 2022 +1030
PR28824, relro security issues, x86 keep COMMONPAGESIZE relro
to use MAXPAGESIZE for the end of the relro segment alignment, like other
ELF targets.
* testsuite/ld-x86-64/plt-main-bnd.dd: Updated.
* testsuite/ld-x86-64/plt-main-ibt-x32.dd: Likewise.
* testsuite/ld-x86-64/plt-main-ibt.dd: Likewise.
* testsuite/ld-x86-64/pr14207.d: Likewise.
* testsuite/ld-x86-64/pr18176.d: Likewise.
* testsuite/ld-x86-64/pr20830a-now.d: Likewise.
* testsuite/ld-x86-64/pr20830a.d: Likewise.
* testsuite/ld-x86-64/pr20830b-now.d: Likewise.
* testsuite/ld-x86-64/pr20830b.d: Likewise.
* testsuite/ld-x86-64/pr21038a-now.d: Likewise.
* testsuite/ld-x86-64/pr21038a.d: Likewise.
* testsuite/ld-x86-64/pr21038b-now.d: Likewise.
* testsuite/ld-x86-64/pr21038b.d: Likewise.
* testsuite/ld-x86-64/pr21038c-now.d: Likewise.
* testsuite/ld-x86-64/pr21038c.d: Likewise.
69 lines
2.0 KiB
Makefile
69 lines
2.0 KiB
Makefile
#name: PR ld/20830 (.plt.got, -z now)
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#source: pr20830.s
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#as: --64
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#ld: -z now -melf_x86_64 -shared -z relro --ld-generated-unwind-info --hash-style=sysv -z max-page-size=0x200000 -z noseparate-code $NO_DT_RELR_LDFLAGS
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#objdump: -dw -Wf
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.*: +file format .*
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Contents of the .eh_frame section:
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0+ 0000000000000014 00000000 CIE
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Version: 1
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Augmentation: "zR"
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Code alignment factor: 1
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Data alignment factor: -8
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Return address column: 16
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Augmentation data: 1b
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DW_CFA_def_cfa: r7 \(rsp\) ofs 8
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DW_CFA_offset: r16 \(rip\) at cfa-8
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DW_CFA_nop
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DW_CFA_nop
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0+18 0000000000000014 0000001c FDE cie=00000000 pc=00000000000001c8..00000000000001d4
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DW_CFA_nop
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DW_CFA_nop
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DW_CFA_nop
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DW_CFA_nop
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DW_CFA_nop
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DW_CFA_nop
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DW_CFA_nop
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0+30 0000000000000024 00000034 FDE cie=00000000 pc=00000000000001b0..00000000000001c0
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DW_CFA_def_cfa_offset: 16
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DW_CFA_advance_loc: 6 to 00000000000001b6
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DW_CFA_def_cfa_offset: 24
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DW_CFA_advance_loc: 10 to 00000000000001c0
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DW_CFA_def_cfa_expression \(DW_OP_breg7 \(rsp\): 8; DW_OP_breg16 \(rip\): 0; DW_OP_lit15; DW_OP_and; DW_OP_lit11; DW_OP_ge; DW_OP_lit3; DW_OP_shl; DW_OP_plus\)
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DW_CFA_nop
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DW_CFA_nop
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DW_CFA_nop
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DW_CFA_nop
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0+58 0000000000000010 0000005c FDE cie=00000000 pc=00000000000001c0..00000000000001c8
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DW_CFA_nop
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DW_CFA_nop
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DW_CFA_nop
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Disassembly of section .plt:
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0+1b0 <.plt>:
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+[a-f0-9]+: ff 35 32 fe 3f 00 push 0x3ffe32\(%rip\) # 3fffe8 <_GLOBAL_OFFSET_TABLE_\+0x8>
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+[a-f0-9]+: ff 25 34 fe 3f 00 jmp \*0x3ffe34\(%rip\) # 3ffff0 <_GLOBAL_OFFSET_TABLE_\+0x10>
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+[a-f0-9]+: 0f 1f 40 00 nopl 0x0\(%rax\)
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Disassembly of section .plt.got:
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0+1c0 <func@plt>:
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+[a-f0-9]+: ff 25 32 fe 3f 00 jmp \*0x3ffe32\(%rip\) # 3ffff8 <func>
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+[a-f0-9]+: 66 90 xchg %ax,%ax
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Disassembly of section .text:
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0+1c8 <foo>:
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+[a-f0-9]+: e8 f3 ff ff ff call 1c0 <func@plt>
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+[a-f0-9]+: 48 8b 05 24 fe 3f 00 mov 0x3ffe24\(%rip\),%rax # 3ffff8 <func>
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#pass
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