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1368b914e9
Now that all port tests live under testsuite/sim/*/, and none live in testsuite/ directly, flatten the structure by moving all of the dirs under testsuite/sim/ to testsuite/ directly. We need to stop passing --tool to dejagnu so that it searches all dirs and not just ones that start with "sim". Since we have no other dirs in this tree, and no plans to add any, should be fine.
111 lines
1.8 KiB
ArmAsm
111 lines
1.8 KiB
ArmAsm
# sh testcase for pdec
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# mach: shdsp
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# as(shdsp): -defsym sim_cpu=1 -dsp
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.include "testutils.inc"
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start
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pdecx:
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set_grs_a5a5
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lds r0, a0
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pcopy a0, a1
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lds r0, x0
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lds r0, x1
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lds r0, y0
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lds r0, y1
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pcopy x0, m0
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pcopy y1, m1
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pdec x0, y0
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assert_sreg 0xa5a40000, y0
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test_grs_a5a5
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assert_sreg 0xa5a5a5a5, x0
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assert_sreg 0xa5a5a5a5, x1
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assert_sreg 0xa5a5a5a5, y1
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assert_sreg 0xa5a5a5a5, a0
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assert_sreg2 0xa5a5a5a5, a1
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assert_sreg2 0xa5a5a5a5, m0
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assert_sreg2 0xa5a5a5a5, m1
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pdecy:
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set_grs_a5a5
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lds r0, a0
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pcopy a0, a1
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lds r0, x0
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lds r0, x1
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lds r0, y0
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lds r0, y1
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pcopy x0, m0
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pcopy y1, m1
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pdec y0, x0
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assert_sreg 0xa5a40000, x0
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test_grs_a5a5
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assert_sreg 0xa5a5a5a5, y0
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assert_sreg 0xa5a5a5a5, x1
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assert_sreg 0xa5a5a5a5, y1
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assert_sreg 0xa5a5a5a5, a0
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assert_sreg2 0xa5a5a5a5, a1
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assert_sreg2 0xa5a5a5a5, m0
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assert_sreg2 0xa5a5a5a5, m1
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dct_pdecx:
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set_grs_a5a5
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lds r0, a0
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pcopy a0, a1
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lds r0, x0
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lds r0, x1
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lds r0, y0
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lds r0, y1
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pcopy x0, m0
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pcopy y1, m1
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set_dcfalse
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dct pdec x0, y0
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assert_sreg 0xa5a5a5a5, y0
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set_dctrue
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dct pdec x0, y0
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assert_sreg 0xa5a40000, y0
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test_grs_a5a5
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assert_sreg 0xa5a5a5a5, x0
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assert_sreg 0xa5a5a5a5, x1
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assert_sreg 0xa5a5a5a5, y1
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assert_sreg 0xa5a5a5a5, a0
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assert_sreg2 0xa5a5a5a5, a1
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assert_sreg2 0xa5a5a5a5, m0
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assert_sreg2 0xa5a5a5a5, m1
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dcf_pdecy:
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set_grs_a5a5
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lds r0, a0
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pcopy a0, a1
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lds r0, x0
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lds r0, x1
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lds r0, y0
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lds r0, y1
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pcopy x0, m0
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pcopy y1, m1
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set_dctrue
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dcf pdec y0, x0
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assert_sreg 0xa5a5a5a5, x0
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set_dcfalse
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dcf pdec y0, x0
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assert_sreg 0xa5a40000, x0
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test_grs_a5a5
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assert_sreg 0xa5a5a5a5, x1
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assert_sreg 0xa5a5a5a5, y0
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assert_sreg 0xa5a5a5a5, y1
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assert_sreg 0xa5a5a5a5, a0
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assert_sreg2 0xa5a5a5a5, a1
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assert_sreg2 0xa5a5a5a5, m0
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assert_sreg2 0xa5a5a5a5, m1
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pass
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exit 0
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