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b9249c461c
binutils-gdb/sim
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Mike Frysinger b9249c461c sim: riscv: new port 
This is a hand-written implementation that should have fairly complete
coverage for the base integer instruction set ("i"), and for the atomic
("a") and integer multiplication+division ("m") extensions.  It also
covers 32-bit & 64-bit targets.

The unittest coverage is a bit weak atm, but should get better.
2021-02-04 19:02:19 -05:00
..
aarch64
arm
avr sim: watchpoints: change sizeof_pc to sizeof(sim_cia) 2021-01-30 10:14:21 -05:00
bfin sim: watchpoints: change sizeof_pc to sizeof(sim_cia) 2021-01-30 10:14:21 -05:00
bpf sim: bpf: fix mainloop extract call 2021-01-31 17:19:38 -05:00
common sim: riscv: new port 2021-02-04 19:02:19 -05:00
cr16
cris
d10v
erc32 sim: call SIM_AC_OPTION_WARNINGS(no) in remaining ports 2021-01-11 09:13:11 -05:00
frv sim: watchpoints: change sizeof_pc to sizeof(sim_cia) 2021-01-30 10:14:21 -05:00
ft32
h8300 sim: h8300: drop separate eightbit memory buffer 2021-01-13 21:54:00 -05:00
igen
iq2000 sim: watchpoints: change sizeof_pc to sizeof(sim_cia) 2021-01-30 10:14:21 -05:00
lm32 sim: call SIM_AC_OPTION_WARNINGS(no) in remaining ports 2021-01-11 09:13:11 -05:00
m32c
m32r sim: watchpoints: change sizeof_pc to sizeof(sim_cia) 2021-01-30 10:14:21 -05:00
m68hc11 sim: m68hc11: fix printf size warnings 2021-01-30 10:40:26 -05:00
mcore
microblaze
mips sim: watchpoints: change sizeof_pc to sizeof(sim_cia) 2021-01-30 10:14:21 -05:00
mn10300 sim: watchpoints: change sizeof_pc to sizeof(sim_cia) 2021-01-30 10:14:21 -05:00
moxie sim: moxie: cleanup build warnings 2021-01-31 12:06:29 -05:00
msp430
or1k sim: bpf/or1k: fix CGEN_TRACE_EXTRACT name 2021-01-31 17:08:49 -05:00
ppc sim: ppc: update version script usage 2021-01-19 10:54:06 -05:00
pru
riscv sim: riscv: new port 2021-02-04 19:02:19 -05:00
rl78 sim: call SIM_AC_OPTION_WARNINGS(no) in remaining ports 2021-01-11 09:13:11 -05:00
rx sim: call SIM_AC_OPTION_WARNINGS(no) in remaining ports 2021-01-11 09:13:11 -05:00
sh
testsuite sim: riscv: new port 2021-02-04 19:02:19 -05:00
v850 sim: v850: cleanup build warnings 2021-01-31 15:19:16 -05:00
.gitignore
ChangeLog sim: riscv: new port 2021-02-04 19:02:19 -05:00
configure sim: riscv: new port 2021-02-04 19:02:19 -05:00
configure.ac sim: common: delete configure & Makefile 2021-01-18 12:23:18 -05:00
configure.tgt sim: riscv: new port 2021-02-04 19:02:19 -05:00
MAINTAINERS sim: readd myself as a maintainer 2021-01-29 22:11:45 -05:00
Makefile.in sim: common: change gennltvals helper to Python 2021-01-30 20:17:46 -05:00
README-HACKING sim: watchpoints: change sizeof_pc to sizeof(sim_cia) 2021-01-30 10:14:21 -05:00