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1368b914e9
Now that all port tests live under testsuite/sim/*/, and none live in testsuite/ directly, flatten the structure by moving all of the dirs under testsuite/sim/ to testsuite/ directly. We need to stop passing --tool to dejagnu so that it searches all dirs and not just ones that start with "sim". Since we have no other dirs in this tree, and no plans to add any, should be fine.
206 lines
5.9 KiB
Plaintext
206 lines
5.9 KiB
Plaintext
# FRV testcase for handling of shadow registers SR0-SR4
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# mach: frv
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.include "testutils.inc"
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start
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.global tra
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tra:
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test_spr_bits 0x800,11,1,psr ; PSR.ESR set
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test_spr_bits 0x4,2,1,psr ; PSR.S set
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; Set up exception handler for later
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and_spr_immed -4081,tbr ; clear tbr.tt
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set_gr_spr tbr,gr7
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inc_gr_immed 2112,gr7 ; address of exception handler
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set_bctrlr_0_0 gr7 ; bctrlr 0,0
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set_spr_immed 128,lcr
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set_psr_et 1
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set_gr_immed 0x11111111,gr4 ; SGR4-7
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set_gr_immed 0x22222222,gr5
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set_gr_immed 0x33333333,gr6
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set_gr_immed 0x44444444,gr7
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set_spr_immed 0x55555555,sr0 ; UGR4-7
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set_spr_immed 0x66666666,sr1
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set_spr_immed 0x77777777,sr2
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set_spr_immed 0x88888888,sr3
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and_spr_immed 0xfffff7ff,psr ; turn off PSR.ESR
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test_gr_immed 0x11111111,gr4 ; SGR4-7
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test_gr_immed 0x22222222,gr5
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test_gr_immed 0x33333333,gr6
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test_gr_immed 0x44444444,gr7
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test_spr_immed 0x11111111,sr0 ; SGR4-7
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test_spr_immed 0x22222222,sr1
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test_spr_immed 0x33333333,sr2
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test_spr_immed 0x44444444,sr3
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set_spr_immed 0x55555555,sr0 ; SGR4-7
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set_spr_immed 0x66666666,sr1
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set_spr_immed 0x77777777,sr2
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set_spr_immed 0x88888888,sr3
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test_gr_immed 0x55555555,gr4 ; SGR4-7
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test_gr_immed 0x66666666,gr5
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test_gr_immed 0x77777777,gr6
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test_gr_immed 0x88888888,gr7
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test_spr_immed 0x55555555,sr0 ; SGR4-7
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test_spr_immed 0x66666666,sr1
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test_spr_immed 0x77777777,sr2
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test_spr_immed 0x88888888,sr3
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set_gr_immed 0x11111111,gr4 ; SGR4-7
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set_gr_immed 0x22222222,gr5
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set_gr_immed 0x33333333,gr6
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set_gr_immed 0x44444444,gr7
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test_gr_immed 0x11111111,gr4 ; SGR4-7
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test_gr_immed 0x22222222,gr5
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test_gr_immed 0x33333333,gr6
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test_gr_immed 0x44444444,gr7
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test_spr_immed 0x11111111,sr0 ; SGR4-7
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test_spr_immed 0x22222222,sr1
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test_spr_immed 0x33333333,sr2
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test_spr_immed 0x44444444,sr3
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or_spr_immed 0x00000800,psr ; turn on PSR.ESR
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test_gr_immed 0x11111111,gr4 ; SGR4-7 -- SR0-3 (UGR4-7) are undefined
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test_gr_immed 0x22222222,gr5
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test_gr_immed 0x33333333,gr6
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test_gr_immed 0x44444444,gr7
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set_spr_immed 0x55555555,sr0 ; UGR4-7
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set_spr_immed 0x66666666,sr1
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set_spr_immed 0x77777777,sr2
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set_spr_immed 0x88888888,sr3
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test_gr_immed 0x11111111,gr4 ; SGR4-7
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test_gr_immed 0x22222222,gr5
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test_gr_immed 0x33333333,gr6
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test_gr_immed 0x44444444,gr7
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test_spr_immed 0x55555555,sr0 ; UGR4-7
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test_spr_immed 0x66666666,sr1
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test_spr_immed 0x77777777,sr2
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test_spr_immed 0x88888888,sr3
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and_spr_immed 0xfffffffb,psr ; turn off PSR.S
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test_spr_immed 0x11111111,sr0 ; SGR4-7
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test_spr_immed 0x22222222,sr1
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test_spr_immed 0x33333333,sr2
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test_spr_immed 0x44444444,sr3
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test_gr_immed 0x55555555,gr4 ; UGR4-7
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test_gr_immed 0x66666666,gr5
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test_gr_immed 0x77777777,gr6
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test_gr_immed 0x88888888,gr7
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; need to generate a trap to return to supervisor mode
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set_spr_addr ok0,lr
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tira gr0,4 ; should branch to tbr + (128 + 4)*16
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test_spr_bits 0x800,11,0,psr ; PSR.ESR clear
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test_spr_bits 0x4,2,0,psr ; PSR.S clear
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test_gr_immed 0x11111111,gr4 ; SGR4-7
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test_gr_immed 0x22222222,gr5
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test_gr_immed 0x33333333,gr6
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test_gr_immed 0x44444444,gr7
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test_spr_immed 0x11111111,sr0 ; SGR4-7
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test_spr_immed 0x22222222,sr1
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test_spr_immed 0x33333333,sr2
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test_spr_immed 0x44444444,sr3
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set_gr_immed 0x55555555,gr4 ; SGR4-7
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set_gr_immed 0x66666666,gr5
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set_gr_immed 0x77777777,gr6
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set_gr_immed 0x88888888,gr7
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test_gr_immed 0x55555555,gr4 ; SGR4-7
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test_gr_immed 0x66666666,gr5
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test_gr_immed 0x77777777,gr6
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test_gr_immed 0x88888888,gr7
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test_spr_immed 0x55555555,sr0 ; SGR4-7
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test_spr_immed 0x66666666,sr1
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test_spr_immed 0x77777777,sr2
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test_spr_immed 0x88888888,sr3
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set_gr_immed 0x11111111,gr4 ; SGR4-7
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set_gr_immed 0x22222222,gr5
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set_gr_immed 0x33333333,gr6
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set_gr_immed 0x44444444,gr7
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test_gr_immed 0x11111111,gr4 ; SGR4-7
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test_gr_immed 0x22222222,gr5
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test_gr_immed 0x33333333,gr6
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test_gr_immed 0x44444444,gr7
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test_spr_immed 0x11111111,sr0 ; SGR4-7
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test_spr_immed 0x22222222,sr1
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test_spr_immed 0x33333333,sr2
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test_spr_immed 0x44444444,sr3
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; need to generate a trap to return to supervisor mode
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set_spr_addr ok1,lr
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tira gr0,4 ; should branch to tbr + (128 + 4)*16
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pass
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ok0: ; exception handler should branch here the first time
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test_spr_bits 0x800,11,1,psr ; PSR.ESR set
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test_spr_bits 0x4,2,1,psr ; PSR.S set
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test_gr_immed 0x11111111,gr4 ; SGR4-7
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test_gr_immed 0x22222222,gr5
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test_gr_immed 0x33333333,gr6
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test_gr_immed 0x44444444,gr7
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test_spr_immed 0x55555555,sr0 ; UGR4-7
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test_spr_immed 0x66666666,sr1
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test_spr_immed 0x77777777,sr2
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test_spr_immed 0x88888888,sr3
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and_spr_immed 0xfffff7ff,psr ; turn off PSR.ESR
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test_gr_immed 0x11111111,gr4 ; SGR4-7
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test_gr_immed 0x22222222,gr5
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test_gr_immed 0x33333333,gr6
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test_gr_immed 0x44444444,gr7
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test_spr_immed 0x11111111,sr0 ; SGR4-7
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test_spr_immed 0x22222222,sr1
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test_spr_immed 0x33333333,sr2
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test_spr_immed 0x44444444,sr3
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rett 0
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fail
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ok1: ; exception handler should branch here the second time
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test_spr_bits 0x800,11,0,psr ; PSR.ESR clear
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test_spr_bits 0x4,2,1,psr ; PSR.S set
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test_gr_immed 0x11111111,gr4 ; SGR4-7
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test_gr_immed 0x22222222,gr5
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test_gr_immed 0x33333333,gr6
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test_gr_immed 0x44444444,gr7
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test_spr_immed 0x11111111,sr0 ; SGR4-7
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test_spr_immed 0x22222222,sr1
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test_spr_immed 0x33333333,sr2
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test_spr_immed 0x44444444,sr3
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set_spr_immed 0x55555555,sr0 ; SGR4-7
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set_spr_immed 0x66666666,sr1
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set_spr_immed 0x77777777,sr2
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set_spr_immed 0x88888888,sr3
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test_gr_immed 0x55555555,gr4 ; SGR4-7
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test_gr_immed 0x66666666,gr5
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test_gr_immed 0x77777777,gr6
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test_gr_immed 0x88888888,gr7
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test_spr_immed 0x55555555,sr0 ; SGR4-7
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test_spr_immed 0x66666666,sr1
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test_spr_immed 0x77777777,sr2
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test_spr_immed 0x88888888,sr3
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set_gr_immed 0x11111111,gr4 ; SGR4-7
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set_gr_immed 0x22222222,gr5
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set_gr_immed 0x33333333,gr6
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set_gr_immed 0x44444444,gr7
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test_gr_immed 0x11111111,gr4 ; SGR4-7
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test_gr_immed 0x22222222,gr5
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test_gr_immed 0x33333333,gr6
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test_gr_immed 0x44444444,gr7
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test_spr_immed 0x11111111,sr0 ; SGR4-7
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test_spr_immed 0x22222222,sr1
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test_spr_immed 0x33333333,sr2
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test_spr_immed 0x44444444,sr3
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rett 0
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fail
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