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https://sourceware.org/git/binutils-gdb.git
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374 lines
8.2 KiB
C
374 lines
8.2 KiB
C
/* Common target dependent code for GDB on ARM systems.
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Copyright (C) 1988-2016 Free Software Foundation, Inc.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#include "common-defs.h"
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#include "common-regcache.h"
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#include "arm.h"
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/* See arm.h. */
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int
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thumb_insn_size (unsigned short inst1)
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{
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if ((inst1 & 0xe000) == 0xe000 && (inst1 & 0x1800) != 0)
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return 4;
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else
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return 2;
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}
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/* See arm.h. */
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int
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bitcount (unsigned long val)
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{
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int nbits;
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for (nbits = 0; val != 0; nbits++)
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val &= val - 1; /* Delete rightmost 1-bit in val. */
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return nbits;
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}
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/* See arm.h. */
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int
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condition_true (unsigned long cond, unsigned long status_reg)
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{
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if (cond == INST_AL || cond == INST_NV)
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return 1;
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switch (cond)
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{
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case INST_EQ:
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return ((status_reg & FLAG_Z) != 0);
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case INST_NE:
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return ((status_reg & FLAG_Z) == 0);
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case INST_CS:
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return ((status_reg & FLAG_C) != 0);
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case INST_CC:
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return ((status_reg & FLAG_C) == 0);
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case INST_MI:
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return ((status_reg & FLAG_N) != 0);
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case INST_PL:
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return ((status_reg & FLAG_N) == 0);
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case INST_VS:
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return ((status_reg & FLAG_V) != 0);
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case INST_VC:
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return ((status_reg & FLAG_V) == 0);
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case INST_HI:
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return ((status_reg & (FLAG_C | FLAG_Z)) == FLAG_C);
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case INST_LS:
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return ((status_reg & (FLAG_C | FLAG_Z)) != FLAG_C);
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case INST_GE:
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return (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0));
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case INST_LT:
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return (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0));
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case INST_GT:
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return (((status_reg & FLAG_Z) == 0)
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&& (((status_reg & FLAG_N) == 0)
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== ((status_reg & FLAG_V) == 0)));
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case INST_LE:
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return (((status_reg & FLAG_Z) != 0)
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|| (((status_reg & FLAG_N) == 0)
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!= ((status_reg & FLAG_V) == 0)));
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}
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return 1;
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}
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/* See arm.h. */
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int
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thumb_advance_itstate (unsigned int itstate)
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{
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/* Preserve IT[7:5], the first three bits of the condition. Shift
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the upcoming condition flags left by one bit. */
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itstate = (itstate & 0xe0) | ((itstate << 1) & 0x1f);
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/* If we have finished the IT block, clear the state. */
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if ((itstate & 0x0f) == 0)
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itstate = 0;
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return itstate;
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}
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/* See arm.h. */
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int
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arm_instruction_changes_pc (uint32_t this_instr)
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{
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if (bits (this_instr, 28, 31) == INST_NV)
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/* Unconditional instructions. */
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switch (bits (this_instr, 24, 27))
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{
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case 0xa:
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case 0xb:
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/* Branch with Link and change to Thumb. */
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return 1;
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case 0xc:
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case 0xd:
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case 0xe:
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/* Coprocessor register transfer. */
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if (bits (this_instr, 12, 15) == 15)
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error (_("Invalid update to pc in instruction"));
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return 0;
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default:
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return 0;
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}
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else
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switch (bits (this_instr, 25, 27))
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{
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case 0x0:
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if (bits (this_instr, 23, 24) == 2 && bit (this_instr, 20) == 0)
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{
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/* Multiplies and extra load/stores. */
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if (bit (this_instr, 4) == 1 && bit (this_instr, 7) == 1)
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/* Neither multiplies nor extension load/stores are allowed
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to modify PC. */
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return 0;
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/* Otherwise, miscellaneous instructions. */
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/* BX <reg>, BXJ <reg>, BLX <reg> */
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if (bits (this_instr, 4, 27) == 0x12fff1
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|| bits (this_instr, 4, 27) == 0x12fff2
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|| bits (this_instr, 4, 27) == 0x12fff3)
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return 1;
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/* Other miscellaneous instructions are unpredictable if they
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modify PC. */
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return 0;
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}
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/* Data processing instruction. Fall through. */
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case 0x1:
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if (bits (this_instr, 12, 15) == 15)
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return 1;
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else
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return 0;
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case 0x2:
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case 0x3:
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/* Media instructions and architecturally undefined instructions. */
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if (bits (this_instr, 25, 27) == 3 && bit (this_instr, 4) == 1)
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return 0;
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/* Stores. */
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if (bit (this_instr, 20) == 0)
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return 0;
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/* Loads. */
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if (bits (this_instr, 12, 15) == ARM_PC_REGNUM)
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return 1;
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else
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return 0;
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case 0x4:
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/* Load/store multiple. */
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if (bit (this_instr, 20) == 1 && bit (this_instr, 15) == 1)
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return 1;
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else
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return 0;
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case 0x5:
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/* Branch and branch with link. */
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return 1;
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case 0x6:
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case 0x7:
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/* Coprocessor transfers or SWIs can not affect PC. */
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return 0;
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default:
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internal_error (__FILE__, __LINE__, _("bad value in switch"));
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}
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}
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/* See arm.h. */
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int
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thumb_instruction_changes_pc (unsigned short inst)
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{
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if ((inst & 0xff00) == 0xbd00) /* pop {rlist, pc} */
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return 1;
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if ((inst & 0xf000) == 0xd000) /* conditional branch */
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return 1;
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if ((inst & 0xf800) == 0xe000) /* unconditional branch */
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return 1;
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if ((inst & 0xff00) == 0x4700) /* bx REG, blx REG */
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return 1;
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if ((inst & 0xff87) == 0x4687) /* mov pc, REG */
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return 1;
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if ((inst & 0xf500) == 0xb100) /* CBNZ or CBZ. */
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return 1;
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return 0;
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}
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/* See arm.h. */
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int
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thumb2_instruction_changes_pc (unsigned short inst1, unsigned short inst2)
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{
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if ((inst1 & 0xf800) == 0xf000 && (inst2 & 0x8000) == 0x8000)
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{
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/* Branches and miscellaneous control instructions. */
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if ((inst2 & 0x1000) != 0 || (inst2 & 0xd001) == 0xc000)
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{
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/* B, BL, BLX. */
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return 1;
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}
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else if (inst1 == 0xf3de && (inst2 & 0xff00) == 0x3f00)
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{
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/* SUBS PC, LR, #imm8. */
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return 1;
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}
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else if ((inst2 & 0xd000) == 0x8000 && (inst1 & 0x0380) != 0x0380)
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{
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/* Conditional branch. */
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return 1;
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}
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return 0;
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}
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if ((inst1 & 0xfe50) == 0xe810)
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{
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/* Load multiple or RFE. */
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if (bit (inst1, 7) && !bit (inst1, 8))
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{
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/* LDMIA or POP */
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if (bit (inst2, 15))
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return 1;
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}
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else if (!bit (inst1, 7) && bit (inst1, 8))
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{
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/* LDMDB */
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if (bit (inst2, 15))
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return 1;
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}
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else if (bit (inst1, 7) && bit (inst1, 8))
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{
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/* RFEIA */
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return 1;
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}
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else if (!bit (inst1, 7) && !bit (inst1, 8))
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{
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/* RFEDB */
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return 1;
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}
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return 0;
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}
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if ((inst1 & 0xffef) == 0xea4f && (inst2 & 0xfff0) == 0x0f00)
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{
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/* MOV PC or MOVS PC. */
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return 1;
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}
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if ((inst1 & 0xff70) == 0xf850 && (inst2 & 0xf000) == 0xf000)
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{
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/* LDR PC. */
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if (bits (inst1, 0, 3) == 15)
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return 1;
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if (bit (inst1, 7))
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return 1;
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if (bit (inst2, 11))
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return 1;
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if ((inst2 & 0x0fc0) == 0x0000)
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return 1;
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return 0;
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}
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if ((inst1 & 0xfff0) == 0xe8d0 && (inst2 & 0xfff0) == 0xf000)
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{
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/* TBB. */
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return 1;
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}
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if ((inst1 & 0xfff0) == 0xe8d0 && (inst2 & 0xfff0) == 0xf010)
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{
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/* TBH. */
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return 1;
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}
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return 0;
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}
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/* See arm.h. */
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unsigned long
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shifted_reg_val (struct regcache *regcache, unsigned long inst,
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int carry, unsigned long pc_val, unsigned long status_reg)
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{
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unsigned long res, shift;
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int rm = bits (inst, 0, 3);
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unsigned long shifttype = bits (inst, 5, 6);
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if (bit (inst, 4))
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{
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int rs = bits (inst, 8, 11);
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shift = (rs == 15
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? pc_val + 8
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: regcache_raw_get_unsigned (regcache, rs)) & 0xFF;
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}
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else
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shift = bits (inst, 7, 11);
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res = (rm == ARM_PC_REGNUM
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? (pc_val + (bit (inst, 4) ? 12 : 8))
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: regcache_raw_get_unsigned (regcache, rm));
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switch (shifttype)
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{
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case 0: /* LSL */
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res = shift >= 32 ? 0 : res << shift;
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break;
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case 1: /* LSR */
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res = shift >= 32 ? 0 : res >> shift;
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break;
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case 2: /* ASR */
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if (shift >= 32)
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shift = 31;
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res = ((res & 0x80000000L)
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? ~((~res) >> shift) : res >> shift);
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break;
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case 3: /* ROR/RRX */
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shift &= 31;
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if (shift == 0)
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res = (res >> 1) | (carry ? 0x80000000L : 0);
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else
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res = (res >> shift) | (res << (32 - shift));
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break;
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}
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return res & 0xffffffff;
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}
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