Stafford Horne 4ea0266c22 Update the openrisc previous program counter (ppc) when running code in the cgen based simulator. ... * or1kcommon.cpu: Add pc set semantics to also update ppc.		2017-03-20 15:33:51 +00:00
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ChangeLog	Update the openrisc previous program counter (ppc) when running code in the cgen based simulator.	2017-03-20 15:33:51 +00:00
cris.cpu
epiphany.cpu	2012-11-30 Oleg Raikhman <oleg@adapteva.com>	2012-11-30 17:54:58 +00:00
epiphany.opc	epiphany/disassembler: Improve alignment of output.	2016-02-02 11:09:17 +00:00
fr30.cpu	Correct fr30 comment	2016-03-03 12:55:30 +10:30
fr30.opc
frv.cpu
frv.opc
ip2k.cpu
ip2k.opc
iq10.cpu
iq2000.cpu
iq2000.opc
iq2000m.cpu
lm32.cpu	PR binutils/15241	2013-03-08 17:25:12 +00:00
lm32.opc
m32c.cpu
m32c.opc
m32r.cpu
m32r.opc
mep-avc2.cpu
mep-avc.cpu
mep-c5.cpu
mep-core.cpu
mep-default.cpu
mep-ext-cop.cpu
mep-fmax.cpu
mep-h1.cpu
mep-ivc2.cpu
mep-rhcop.cpu
mep-sample-ucidsp.cpu
mep.cpu
mep.opc	Add fall through comment to source in cpu/	2016-10-06 22:48:37 +10:30
mt.cpu
mt.opc
or1k.cpu	Remove support for the (deprecated) openrisc and or32 configurations and replace	2014-04-22 15:57:47 +01:00
or1k.opc	Whitespace fixes for cpu/or1k.opc	2014-06-12 12:30:57 +09:30
or1kcommon.cpu	Update the openrisc previous program counter (ppc) when running code in the cgen based simulator.	2017-03-20 15:33:51 +00:00
or1korbis.cpu	or1k: add missing l.msync, l.psync and l.psync instructions.	2014-07-20 20:26:09 +03:00
or1korfpx.cpu	Remove support for the (deprecated) openrisc and or32 configurations and replace	2014-04-22 15:57:47 +01:00
sh64-compact.cpu
sh64-media.cpu
sh.cpu
sh.opc
simplify.inc
xc16x.cpu
xc16x.opc
xstormy16.cpu
xstormy16.opc