mirror/binutils-gdb
2
0
Fork 0
mirror of https://sourceware.org/git/binutils-gdb.git synced 2025-02-11 13:02:10 +08:00
Code Issues Packages Projects Releases Wiki Activity
b78b3a297b
binutils-gdb/opcodes
History
Przemyslaw Wirkus dd4a72c859 aarch64: Add CSR PDEC instruction 
This patch adds:
+ New feature +csre to -march command line.
+ New instruction CSR PDEC associated with CSRE feature.

Please note that CSRE system registers were already upstreamed. This patch
should finalize CSRE feature implementation.

CSRE feature adds CSR PDEC (Decrements Call stack pointer by the size of
a Call stack record) instruction. Although this instruction has operand
(PDEC) it's instruction's only operand. PDEC forces instruction field Rt
to be set to 0b1111. This results in fixed opcode of the instruction.

gas/ChangeLog:

2020-10-27  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>

	* NEWS: Update docs.
	* config/tc-aarch64.c (parse_csr_operand): New operand parser.
	(parse_operands): Call to CSR operand parser.
	* testsuite/gas/aarch64/csre_csr-invalid.d: New test.
	* testsuite/gas/aarch64/csre_csr-invalid.l: New test.
	* testsuite/gas/aarch64/csre_csr-invalid.s: New test.
	* testsuite/gas/aarch64/csre_csr.d: New test.
	* testsuite/gas/aarch64/csre_csr.s: New test.

include/ChangeLog:

2020-10-27  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>

	* opcode/aarch64.h (AARCH64_FEATURE_CSRE): New -march feature.
	(enum aarch64_opnd): New CSR instruction field AARCH64_OPND_CSRE_CSR.

opcodes/ChangeLog:

2020-10-27  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>

	* aarch64-opc.c (aarch64_print_operand): CSR PDEC operand print-out.
	* aarch64-tbl.h (CSRE): New CSRE feature handler.
	(_CSRE_INSN): New CSRE instruction type.
	(struct aarch64_opcode): New 'csre' entry for a CSRE CLI feature.
	* aarch64-asm-2.c: Regenerated.
	* aarch64-dis-2.c: Regenerated.
	* aarch64-opc-2.c: Regenerated.
2020-10-28 14:19:42 +00:00
..
po opcodes/po/es.po: Remove the duplicated entry 2020-10-22 05:21:35 -07:00
.gitignore
aarch64-asm-2.c aarch64: Add CSR PDEC instruction 2020-10-28 14:19:42 +00:00
aarch64-asm.c aarch64: Add DSB instruction Armv8.7-a variant 2020-10-28 14:05:05 +00:00
aarch64-asm.h aarch64: Add DSB instruction Armv8.7-a variant 2020-10-28 14:05:05 +00:00
aarch64-dis-2.c aarch64: Add CSR PDEC instruction 2020-10-28 14:19:42 +00:00
aarch64-dis.c aarch64: Add DSB instruction Armv8.7-a variant 2020-10-28 14:05:05 +00:00
aarch64-dis.h aarch64: Add DSB instruction Armv8.7-a variant 2020-10-28 14:05:05 +00:00
aarch64-gen.c
aarch64-opc-2.c aarch64: Add CSR PDEC instruction 2020-10-28 14:19:42 +00:00
aarch64-opc.c aarch64: Add CSR PDEC instruction 2020-10-28 14:19:42 +00:00
aarch64-opc.h aarch64: Add DSB instruction Armv8.7-a variant 2020-10-28 14:05:05 +00:00
aarch64-tbl.h aarch64: Add CSR PDEC instruction 2020-10-28 14:19:42 +00:00
aclocal.m4
alpha-dis.c
alpha-opc.c
arc-dis.c
arc-dis.h
arc-ext-tbl.h
arc-ext.c
arc-ext.h
arc-fxi.h
arc-nps400-tbl.h
arc-opc.c
arc-regs.h
arc-tbl.h
arm-dis.c
avr-dis.c
bfin-dis.c ubsan: bfin-dis.c:160 shift exponent 32 is too large 2020-09-02 16:30:44 +09:30
bpf-asm.c
bpf-desc.c bpf: xBPF SDIV, SMOD instructions 2020-09-18 10:04:23 -07:00
bpf-desc.h bpf: xBPF SDIV, SMOD instructions 2020-09-18 10:04:23 -07:00
bpf-dis.c
bpf-ibld.c ubsan: *-ibld.c 2020-09-02 16:30:44 +09:30
bpf-opc.c bpf: xBPF SDIV, SMOD instructions 2020-09-18 10:04:23 -07:00
bpf-opc.h bpf: xBPF SDIV, SMOD instructions 2020-09-18 10:04:23 -07:00
cgen-asm.c Fix spelling mistakes 2020-10-05 14:20:15 +01:00
cgen-asm.in
cgen-bitset.c
cgen-dis.c Fix spelling mistakes 2020-10-05 14:20:15 +01:00
cgen-dis.in
cgen-ibld.in ubsan: *-ibld.c 2020-09-02 16:30:44 +09:30
cgen-opc.c
cgen.sh
ChangeLog CSKY: Change plsl.u16 to plsl.16. 2020-10-26 16:26:32 +08:00
ChangeLog-0001
ChangeLog-0203
ChangeLog-2004
ChangeLog-2005
ChangeLog-2006
ChangeLog-2007
ChangeLog-2008
ChangeLog-2009
ChangeLog-2010
ChangeLog-2011
ChangeLog-2012
ChangeLog-2013
ChangeLog-2014
ChangeLog-2015
ChangeLog-2016
ChangeLog-2017
ChangeLog-2018
ChangeLog-2019
ChangeLog-9297
ChangeLog-9899
config.in
configure
configure.ac
configure.com
cr16-dis.c cr16 disassembly error of disp20 fields 2020-08-30 20:49:32 +09:30
cr16-opc.c
cris-dis.c
cris-opc.c
crx-dis.c ubsan: crx-dis.c:571 left shift of negative value 2020-09-02 16:30:44 +09:30
crx-opc.c
csky-dis.c CSKY: Fix and add some instructions for VDSPV1. 2020-10-26 16:13:55 +08:00
csky-opc.h CSKY: Change plsl.u16 to plsl.16. 2020-10-26 16:26:32 +08:00
d10v-dis.c
d10v-opc.c
d30v-dis.c
d30v-opc.c
dep-in.sed
dis-buf.c
dis-init.c
disassemble.c opcodes: Add missing entries to ebpf_isa_attr 2020-08-26 16:48:39 +02:00
disassemble.h
dlx-dis.c
epiphany-asm.c
epiphany-desc.c
epiphany-desc.h
epiphany-dis.c
epiphany-ibld.c ubsan: *-ibld.c 2020-09-02 16:30:44 +09:30
epiphany-opc.c
epiphany-opc.h
fr30-asm.c
fr30-desc.c
fr30-desc.h
fr30-dis.c
fr30-ibld.c ubsan: *-ibld.c 2020-09-02 16:30:44 +09:30
fr30-opc.c
fr30-opc.h
frv-asm.c
frv-desc.c
frv-desc.h
frv-dis.c
frv-ibld.c ubsan: *-ibld.c 2020-09-02 16:30:44 +09:30
frv-opc.c
frv-opc.h
ft32-dis.c
ft32-opc.c
h8300-dis.c
hppa-dis.c
i386-dis-evex-len.h
i386-dis-evex-mod.h
i386-dis-evex-prefix.h
i386-dis-evex-reg.h
i386-dis-evex-w.h
i386-dis-evex.h
i386-dis.c Change avxvnni disassembler output from {vex3} to {vex} 2020-10-26 10:51:55 +08:00
i386-gen.c Add AMD znver3 processor support 2020-10-20 13:58:04 -07:00
i386-init.h Add AMD znver3 processor support 2020-10-20 13:58:04 -07:00
i386-opc.c
i386-opc.h Add AMD znver3 processor support 2020-10-20 13:58:04 -07:00
i386-opc.tbl Add AMD znver3 processor support 2020-10-20 13:58:04 -07:00
i386-reg.tbl
i386-tbl.h Add AMD znver3 processor support 2020-10-20 13:58:04 -07:00
ia64-asmtab.c
ia64-asmtab.h
ia64-dis.c
ia64-gen.c
ia64-ic.tbl
ia64-opc-a.c
ia64-opc-b.c
ia64-opc-d.c
ia64-opc-f.c
ia64-opc-i.c
ia64-opc-m.c
ia64-opc-x.c
ia64-opc.c
ia64-opc.h
ia64-raw.tbl
ia64-war.tbl
ia64-waw.tbl
ip2k-asm.c
ip2k-desc.c
ip2k-desc.h
ip2k-dis.c
ip2k-ibld.c ubsan: *-ibld.c 2020-09-02 16:30:44 +09:30
ip2k-opc.c
ip2k-opc.h
iq2000-asm.c
iq2000-desc.c
iq2000-desc.h
iq2000-dis.c
iq2000-ibld.c ubsan: *-ibld.c 2020-09-02 16:30:44 +09:30
iq2000-opc.c
iq2000-opc.h
lm32-asm.c
lm32-desc.c
lm32-desc.h
lm32-dis.c
lm32-ibld.c ubsan: *-ibld.c 2020-09-02 16:30:44 +09:30
lm32-opc.c
lm32-opc.h
lm32-opinst.c
m32c-asm.c
m32c-desc.c
m32c-desc.h
m32c-dis.c
m32c-ibld.c ubsan: *-ibld.c 2020-09-02 16:30:44 +09:30
m32c-opc.c
m32c-opc.h
m32r-asm.c
m32r-desc.c
m32r-desc.h
m32r-dis.c
m32r-ibld.c ubsan: *-ibld.c 2020-09-02 16:30:44 +09:30
m32r-opc.c
m32r-opc.h
m32r-opinst.c
m68hc11-dis.c
m68hc11-opc.c
m68k-dis.c
m68k-opc.c
m10200-dis.c
m10200-opc.c
m10300-dis.c
m10300-opc.c
MAINTAINERS
Makefile.am
Makefile.in
makefile.vms
mcore-dis.c
mcore-opc.h
mep-asm.c
mep-desc.c
mep-desc.h
mep-dis.c
mep-ibld.c ubsan: *-ibld.c 2020-09-02 16:30:44 +09:30
mep-opc.c
mep-opc.h
metag-dis.c
microblaze-dis.c
microblaze-dis.h
microblaze-opc.h
microblaze-opcm.h
micromips-opc.c
mips16-opc.c
mips-dis.c
mips-formats.h
mips-opc.c
mmix-dis.c
mmix-opc.c
moxie-dis.c
moxie-opc.c
msp430-decode.c
msp430-decode.opc
msp430-dis.c
mt-asm.c
mt-desc.c
mt-desc.h
mt-dis.c
mt-ibld.c ubsan: *-ibld.c 2020-09-02 16:30:44 +09:30
mt-opc.c
mt-opc.h
nds32-asm.c
nds32-asm.h
nds32-dis.c
nds32-opc.h
nfp-dis.c
nios2-dis.c
nios2-opc.c
ns32k-dis.c
opc2c.c
opintl.h
or1k-asm.c
or1k-desc.c
or1k-desc.h
or1k-dis.c
or1k-ibld.c ubsan: *-ibld.c 2020-09-02 16:30:44 +09:30
or1k-opc.c
or1k-opc.h
or1k-opinst.c
pdp11-dis.c
pdp11-opc.c
pj-dis.c
pj-opc.c
ppc-dis.c Tidy elf_symbol_from 2020-09-16 16:41:33 +09:30
ppc-opc.c Correct vcmpsq, vcmpuq and xvtlsbb BF field 2020-08-19 08:47:35 +09:30
pru-dis.c
pru-opc.c
riscv-dis.c
riscv-opc.c
rl78-decode.c
rl78-decode.opc
rl78-dis.c
rx-decode.c
rx-decode.opc
rx-dis.c rx-dis.c:103:3: suspicious concatenation of string literals 2020-09-21 18:20:58 +09:30
s12z-dis.c
s12z-opc.c
s12z-opc.h
s390-dis.c
s390-mkopc.c
s390-opc.c
s390-opc.txt
score7-dis.c
score-dis.c
score-opc.h
sh-dis.c
sh-opc.h
sparc-dis.c
sparc-opc.c
spu-dis.c
spu-opc.c
stamp-h.in
sysdep.h
tic4x-dis.c
tic6x-dis.c
tic30-dis.c Fix spelling mistakes 2020-10-05 14:20:15 +01:00
tic54x-dis.c
tic54x-opc.c
tilegx-dis.c
tilegx-opc.c
tilepro-dis.c
tilepro-opc.c
v850-dis.c
v850-opc.c ubsan: v850-opc.c:412 left shift cannot be represented 2020-09-02 16:30:44 +09:30
vax-dis.c PR26504, ASAN: parse_disassembler_options vax-dis.c:142 2020-08-25 23:07:10 +09:30
visium-dis.c
visium-opc.c
wasm32-dis.c
xc16x-asm.c
xc16x-desc.c
xc16x-desc.h
xc16x-dis.c
xc16x-ibld.c ubsan: *-ibld.c 2020-09-02 16:30:44 +09:30
xc16x-opc.c
xc16x-opc.h
xgate-dis.c
xgate-opc.c
xstormy16-asm.c
xstormy16-desc.c
xstormy16-desc.h
xstormy16-dis.c
xstormy16-ibld.c ubsan: *-ibld.c 2020-09-02 16:30:44 +09:30
xstormy16-opc.c
xstormy16-opc.h
xtensa-dis.c
z8k-dis.c
z8k-opc.h Z8k: fix sout/soudb opcodes with direct address 2020-08-04 22:31:42 +02:00
z8kgen.c Z8k: fix sout/soudb opcodes with direct address 2020-08-04 22:31:42 +02:00
z80-dis.c