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b4e87f2c1e
We currently use a padding NOP after a Thumb to Arm interworking veneer (BX pc). The NOP is never executed but may result in a performance penalty on some cores. For this reason this patch changes the NOPs after Thumb to Arm veneers into B .-2 and adds a note to this in the source code for future reference. bfd/ChangeLog: * elf32-arm.c (elf32_thumb2_plt_entry, elf32_arm_plt_thumb_stub, elf32_arm_stub_long_branch_v4t_thumb_thumb, elf32_arm_stub_long_branch_v4t_thumb_arm, elf32_arm_stub_short_branch_v4t_thumb_arm, elf32_arm_stub_long_branch_v4t_thumb_arm_pic, elf32_arm_stub_long_branch_v4t_thumb_thumb_pic, elf32_arm_stub_long_branch_v4t_thumb_tls_pic): Change nop to branch to previous instruction. ld/ChangeLog: * testsuite/ld-arm/cortex-a8-fix-b-plt.d: Update Testcase. * testsuite/ld-arm/cortex-a8-fix-b-rel-arm.d: Likewise. * testsuite/ld-arm/cortex-a8-fix-bcc-plt.d: Likewise. * testsuite/ld-arm/farcall-cond-thumb-arm.d: Likewise. * testsuite/ld-arm/farcall-mixed-app.d: Likewise. * testsuite/ld-arm/farcall-mixed-app2.d: Likewise. * testsuite/ld-arm/farcall-mixed-lib-v4t.d: Likewise. * testsuite/ld-arm/farcall-thumb-arm-pic-veneer.d: Likewise. * testsuite/ld-arm/farcall-thumb-arm-short.d: Likewise. * testsuite/ld-arm/farcall-thumb-arm.d: Likewise. * testsuite/ld-arm/farcall-thumb-thumb-pic-veneer.d: Likewise. * testsuite/ld-arm/farcall-thumb-thumb.d: Likewise. * testsuite/ld-arm/fix-arm1176-on.d: Likewise. * testsuite/ld-arm/ifunc-10.dd: Likewise. * testsuite/ld-arm/ifunc-2.dd: Likewise. * testsuite/ld-arm/ifunc-4.dd: Likewise. * testsuite/ld-arm/ifunc-6.dd: Likewise. * testsuite/ld-arm/ifunc-8.dd: Likewise. * testsuite/ld-arm/jump-reloc-veneers-long.d: Likewise. * testsuite/ld-arm/mixed-app.d: Likewise. * testsuite/ld-arm/thumb2-b-interwork.d: Likewise. * testsuite/ld-arm/tls-longplt.d: Likewise. * testsuite/ld-arm/tls-thumb1.d: Likewise.
65 lines
1.9 KiB
Makefile
65 lines
1.9 KiB
Makefile
.*: file format elf32-.*arm
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architecture: armv6t2, flags 0x00000112:
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EXEC_P, HAS_SYMS, D_PAGED
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start address 0x.*
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Disassembly of section .plt:
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0000819c <.plt>:
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819c: e52de004 push {lr} ; .*
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81a0: e59fe004 ldr lr, \[pc, #4\] ; .*
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81a4: e08fe00e add lr, pc, lr
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81a8: e5bef008 ldr pc, \[lr, #8\]!
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81ac: 00008100 .word 0x00008100
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81b0: e08e0000 add r0, lr, r0
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81b4: e5901004 ldr r1, \[r0, #4]
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81b8: e12fff11 bx r1
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81bc: e52d2004 push {r2} ; .*
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81c0: e59f200c ldr r2, \[pc, #12\] ; .*
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81c4: e59f100c ldr r1, \[pc, #12\] ; .*
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81c8: e79f2002 ldr r2, \[pc, r2\]
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81cc: e081100f add r1, r1, pc
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81d0: e12fff12 bx r2
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81d4: 000080f4 .word 0x000080f4
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81d8: 000080d8 .word 0x000080d8
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Disassembly of section .text:
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000081dc <text>:
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81dc: e59f0004 ldr r0, \[pc, #4\] ; .*
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81e0: fafffff2 blx 81b0 .*
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81e4: e1a00000 nop ; .*
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81e8: 000080d4 .word 0x000080d4
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81ec: 4801 ldr r0, \[pc, #4\] ; .*
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81ee: f7ff efe0 blx 81b0 .*
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81f2: bf00 nop
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81f4: 000080c5 .word 0x000080c5
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Disassembly of section .foo:
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04001000 <foo>:
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4001000: e59f0004 ldr r0, \[pc, #4\] ; .*
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4001004: e79f0000 ldr r0, \[pc, r0\]
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4001008: e1a00000 nop ; .*
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400100c: fc00f2b4 .word 0xfc00f2b4
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4001010: e59f0004 ldr r0, \[pc, #4\] ; .*
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4001014: fa000005 blx 4001030 .*
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4001018: e1a00000 nop ; .*
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400101c: fc00f2a0 .word 0xfc00f2a0
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4001020: 4801 ldr r0, \[pc, #4\] ; .*
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4001022: f000 f809 bl 4001038 .*
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4001026: bf00 nop
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4001028: fc00f291 .word 0xfc00f291
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400102c: 00000000 .word 0x00000000
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04001030 <__unnamed_veneer>:
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4001030: e51ff004 ldr pc, \[pc, #-4\] ; .*
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4001034: 000081b0 .word 0x000081b0
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04001038 <__unnamed_veneer>:
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4001038: 4778 bx pc
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400103a: e7fd b.n .+ <.+>
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400103c: e51ff004 ldr pc, \[pc, #-4\] ; .*
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4001040: 000081b0 .word 0x000081b0
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4001044: 00000000 .word 0x00000000
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