binutils-gdb/include/opcode
Jan Beulich 21df382b91 x86: fold SReg{2,3}
They're the only exception to there generally being no mix of register
kinds possible in an insn operand template, and there being two bits per
operand for their representation is also quite wasteful, considering the
low number of uses.  Fold both bits and deal with the little bit of
fallout.

Also take the liberty and drop dead code trying to set REX_B: No segment
register has RegRex set on it.

Additionally I was quite surprised that PUSH/POP with the permitted
segment registers is not covered by the test cases.  Add the missing
pieces.
2019-07-16 09:30:29 +02:00
..
aarch64.h [gas][aarch64][SVE2] Fix pmull{t,b} requirement on SVE2-AES 2019-07-01 15:17:22 +01:00
alpha.h
arc-attrs.h
arc-func.h
arc.h
arm.h [PATCH 1/57][Arm][GAS]: Add support for +mve and +mve.fp 2019-05-16 16:17:21 +01:00
avr.h
bfin.h
cgen.h
ChangeLog-0415
ChangeLog-9103
convex.h
cr16.h
cris.h
crx.h
csky.h
d10v.h
d30v.h
dlx.h
ft32.h
h8300.h
hppa.h
i386.h x86: fold SReg{2,3} 2019-07-16 09:30:29 +02:00
ia64.h
m68hc11.h
m68k.h
metag.h
mips.h Add load-link, store-conditional paired EVA instructions 2019-05-06 06:43:32 -07:00
mmix.h
mn10200.h
mn10300.h
moxie.h
msp430-decode.h
msp430.h
nds32.h
nfp.h
nios2.h
nios2r1.h
nios2r2.h
np1.h
ns32k.h
pdp11.h
pj.h
pn.h
ppc.h PowerPC add initial -mfuture instruction support 2019-05-24 10:24:45 +09:30
pru.h
pyr.h
riscv-opc.h
riscv.h
rl78.h
rx.h
s12z.h
s390.h
score-datadep.h
score-inst.h
sparc.h
spu-insns.h
spu.h
tic4x.h
tic6x-control-registers.h
tic6x-insn-formats.h
tic6x-opcode-table.h
tic6x.h
tic30.h
tic54x.h
tic80.h
tilegx.h
tilepro.h
v850.h
vax.h
visium.h
wasm.h
xgate.h